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mailing list for the eCos project.
Re: PPC serial - fix buffer allocation
On Fri, 2003-03-28 at 10:38, Jonathan Larmour wrote:
> Gary Thomas wrote:
> > On Fri, 2003-03-28 at 09:21, Jonathan Larmour wrote:
> >
> >>Gary Thomas wrote:
> >>
> >>>Index: devs/serial/powerpc/quicc/current/ChangeLog
> >>>===================================================================
> >>>RCS file: /misc/cvsfiles/ecos/packages/devs/serial/powerpc/quicc/current/ChangeLog,v
> >>>retrieving revision 1.16
> >>>diff -u -5 -p -r1.16 ChangeLog
> >>>--- devs/serial/powerpc/quicc/current/ChangeLog 23 Mar 2003 16:21:40 -0000 1.16
> >>>+++ devs/serial/powerpc/quicc/current/ChangeLog 28 Mar 2003 13:14:15 -0000
> >>>@@ -1,5 +1,10 @@
> >>>+2003-03-28 Gary Thomas <gary at mlbassoc dot com>
> >>>+
> >>>+ * src/quicc_smc_serial.c: Change how buffers are allocated & aligned
> >>>+ to a cache line - previous attempt wasted a huge amount of space.
> >>
> >>Wouldn't it be (potentially) more efficient still to use an alignment macro?
> >
> >
> > It might, but I seem to recall that there are limits on the
> > granularity of the alignment (the linker will only go so far
> > for non-section objects).
>
> I don't recall that happening, and from a quick test with:
>
> #include <stdio.h>
>
> char one;
> char foo[7777] __attribute__((aligned(1024)));
>
> int main()
> {
> printf("&one=%p, &foo=%p\n", &one, &foo);
> return 0;
> }
>
> it doesn't appear to either.
OK, you've convinced me :-) Here's the changes to use the
__align__ constraint instead.
Index: devs/eth/powerpc/fec/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/eth/powerpc/fec/current/ChangeLog,v
retrieving revision 1.16
diff -u -5 -p -r1.16 ChangeLog
--- devs/eth/powerpc/fec/current/ChangeLog 28 Mar 2003 13:11:52 -0000 1.16
+++ devs/eth/powerpc/fec/current/ChangeLog 28 Mar 2003 18:20:00 -0000
@@ -1,10 +1,10 @@
2003-03-28 Gary Thomas <gary at mlbassoc dot com>
* src/if_fec.c: Use new CPM/DPRAM buffer allocation scheme. Also,
- better handling when aligning buffers to cache lines.
-
+ better handling when aligning buffers to cache lines.
+
2003-01-20 Gary Thomas <gary at mlbassoc dot com>
* cdl/fec_eth_drivers.cdl: Increase number of allowed buffers.
2002-11-14 Gary Thomas <gthomas at ecoscentric dot com>
Index: devs/eth/powerpc/fec/current/src/if_fec.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/eth/powerpc/fec/current/src/if_fec.c,v
retrieving revision 1.15
diff -u -5 -p -r1.15 if_fec.c
--- devs/eth/powerpc/fec/current/src/if_fec.c 28 Mar 2003 13:11:52 -0000 1.15
+++ devs/eth/powerpc/fec/current/src/if_fec.c 28 Mar 2003 18:18:21 -0000
@@ -77,16 +77,14 @@
#include <cyg/io/eth/eth_drv.h>
#include "fec.h"
// Align buffers on a cache boundary
-#define CACHE_ALIGN(b) (((unsigned long)(b) + (HAL_DCACHE_LINE_SIZE-1)) & ~(HAL_DCACHE_LINE_SIZE-1))
-
-#define RxBUFSIZE CYGNUM_DEVS_ETH_POWERPC_FEC_RxNUM*CYGNUM_DEVS_ETH_POWERPC_FEC_BUFSIZE+HAL_DCACHE_LINE_SIZE
-#define TxBUFSIZE CYGNUM_DEVS_ETH_POWERPC_FEC_TxNUM*CYGNUM_DEVS_ETH_POWERPC_FEC_BUFSIZE+HAL_DCACHE_LINE_SIZE
-static unsigned char fec_eth_rxbufs[RxBUFSIZE];
-static unsigned char fec_eth_txbufs[TxBUFSIZE];
+#define RxBUFSIZE CYGNUM_DEVS_ETH_POWERPC_FEC_RxNUM*CYGNUM_DEVS_ETH_POWERPC_FEC_BUFSIZE
+#define TxBUFSIZE CYGNUM_DEVS_ETH_POWERPC_FEC_TxNUM*CYGNUM_DEVS_ETH_POWERPC_FEC_BUFSIZE
+static unsigned char fec_eth_rxbufs[RxBUFSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
+static unsigned char fec_eth_txbufs[TxBUFSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
static struct fec_eth_info fec_eth0_info;
static unsigned char _default_enaddr[] = { 0x08, 0x00, 0x3E, 0x28, 0x7A, 0xBA};
static unsigned char enaddr[6];
#ifdef CYGPKG_REDBOOT
@@ -294,12 +292,12 @@ fec_eth_reset(struct eth_drv_sc *sc, uns
rxbd = (struct fec_bd *)(RxBD + (cyg_uint32)eppc);
qi->tbase = qi->txbd = qi->tnext = txbd;
qi->rbase = qi->rxbd = qi->rnext = rxbd;
qi->txactive = 0;
- RxBUF = (unsigned char *)CACHE_ALIGN(&fec_eth_rxbufs[0]);
- TxBUF = (unsigned char *)CACHE_ALIGN(&fec_eth_txbufs[0]);
+ RxBUF = &fec_eth_rxbufs[0];
+ TxBUF = &fec_eth_txbufs[0];
// setup buffer descriptors
for (i = 0; i < CYGNUM_DEVS_ETH_POWERPC_FEC_RxNUM; i++) {
rxbd->length = 0;
rxbd->buffer = RxBUF;
Index: devs/eth/powerpc/quicc/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/eth/powerpc/quicc/current/ChangeLog,v
retrieving revision 1.18
diff -u -5 -p -r1.18 ChangeLog
--- devs/eth/powerpc/quicc/current/ChangeLog 17 Mar 2003 18:35:38 -0000 1.18
+++ devs/eth/powerpc/quicc/current/ChangeLog 28 Mar 2003 18:19:39 -0000
@@ -1,5 +1,9 @@
+2003-03-28 Gary Thomas <gary at mlbassoc dot com>
+
+ * src/if_quicc.c: Align data buffers on cache boundary.
+
2003-03-14 Nick Garnett <nickg at calivar dot com>
* src/if_quicc.c: Fixed several bugs, mostly dealing with getting
the device restarted after certain failures such as collisions.
Index: devs/eth/powerpc/quicc/current/src/if_quicc.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/eth/powerpc/quicc/current/src/if_quicc.c,v
retrieving revision 1.18
diff -u -5 -p -r1.18 if_quicc.c
--- devs/eth/powerpc/quicc/current/src/if_quicc.c 21 Mar 2003 18:18:52 -0000 1.18
+++ devs/eth/powerpc/quicc/current/src/if_quicc.c 28 Mar 2003 18:17:23 -0000
@@ -85,13 +85,13 @@
#include <cyg/io/eth/eth_drv.h>
#include "quicc_eth.h"
static unsigned char quicc_eth_rxbufs[CYGNUM_DEVS_ETH_POWERPC_QUICC_RxNUM]
- [CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE];
+ [CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
static unsigned char quicc_eth_txbufs[CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM]
- [CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE];
+ [CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
static struct quicc_eth_info quicc_eth0_info;
static unsigned char _default_enaddr[] = { 0x08, 0x00, 0x3E, 0x28, 0x79, 0xB8};
static unsigned char enaddr[6];
#ifdef CYGPKG_REDBOOT
Index: devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c,v
retrieving revision 1.13
diff -u -5 -p -r1.13 quicc_smc_serial.c
--- devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c 28 Mar 2003 13:14:39 -0000 1.13
+++ devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c 28 Mar 2003 18:17:21 -0000
@@ -63,13 +63,10 @@
#include <cyg/hal/quicc/ppc8xx.h>
#include CYGBLD_HAL_PLATFORM_H
#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC
-// macro for aligning buffers to cache lines
-#define ALIGN_TO_CACHELINES(b) ((cyg_uint8 *)(((CYG_ADDRESS)(b) + (HAL_DCACHE_LINE_SIZE-1)) & ~(HAL_DCACHE_LINE_SIZE-1)))
-
#include "quicc_smc_serial.h"
typedef struct quicc_sxx_serial_info {
CYG_ADDRWORD channel; // Which channel SMCx/SCCx
short int_num; // Interrupt number
@@ -138,12 +135,12 @@ static SERIAL_CHANNEL(quicc_sxx_serial_c
CYG_SERIAL_WORD_LENGTH_DEFAULT,
CYG_SERIAL_FLAGS_DEFAULT
);
#endif
-static unsigned char quicc_smc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE+HAL_DCACHE_LINE_SIZE];
-static unsigned char quicc_smc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE+HAL_DCACHE_LINE_SIZE];
+static unsigned char quicc_smc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
+static unsigned char quicc_smc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
DEVTAB_ENTRY(quicc_smc_serial_io_smc1,
CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_NAME,
0, // Does not depend on a lower level interface
&cyg_io_serial_devio,
@@ -183,12 +180,12 @@ static SERIAL_CHANNEL(quicc_sxx_serial_c
CYG_SERIAL_PARITY_DEFAULT,
CYG_SERIAL_WORD_LENGTH_DEFAULT,
CYG_SERIAL_FLAGS_DEFAULT
);
#endif
-static unsigned char quicc_smc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE+HAL_DCACHE_LINE_SIZE];
-static unsigned char quicc_smc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE+HAL_DCACHE_LINE_SIZE];
+static unsigned char quicc_smc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
+static unsigned char quicc_smc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
DEVTAB_ENTRY(quicc_smc_serial_io_smc2,
CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_NAME,
0, // Does not depend on a lower level interface
&cyg_io_serial_devio,
@@ -228,12 +225,12 @@ static SERIAL_CHANNEL(quicc_sxx_serial_c
CYG_SERIAL_PARITY_DEFAULT,
CYG_SERIAL_WORD_LENGTH_DEFAULT,
CYG_SERIAL_FLAGS_DEFAULT
);
#endif
-static unsigned char quicc_scc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxSIZE+HAL_DCACHE_LINE_SIZE];
-static unsigned char quicc_scc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxSIZE+HAL_DCACHE_LINE_SIZE];
+static unsigned char quicc_scc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
+static unsigned char quicc_scc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
DEVTAB_ENTRY(quicc_smc_serial_io_scc1,
CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_NAME,
0, // Does not depend on a lower level interface
&cyg_io_serial_devio,
@@ -273,12 +270,12 @@ static SERIAL_CHANNEL(quicc_sxx_serial_c
CYG_SERIAL_PARITY_DEFAULT,
CYG_SERIAL_WORD_LENGTH_DEFAULT,
CYG_SERIAL_FLAGS_DEFAULT
);
#endif
-static unsigned char quicc_scc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxSIZE+HAL_DCACHE_LINE_SIZE];
-static unsigned char quicc_scc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxSIZE+HAL_DCACHE_LINE_SIZE];
+static unsigned char quicc_scc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
+static unsigned char quicc_scc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
DEVTAB_ENTRY(quicc_smc_serial_io_scc2,
CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_NAME,
0, // Does not depend on a lower level interface
&cyg_io_serial_devio,
@@ -318,12 +315,12 @@ static SERIAL_CHANNEL(quicc_sxx_serial_c
CYG_SERIAL_PARITY_DEFAULT,
CYG_SERIAL_WORD_LENGTH_DEFAULT,
CYG_SERIAL_FLAGS_DEFAULT
);
#endif
-static unsigned char quicc_scc3_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxSIZE+HAL_DCACHE_LINE_SIZE];
-static unsigned char quicc_scc3_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxSIZE+HAL_DCACHE_LINE_SIZE];
+static unsigned char quicc_scc3_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
+static unsigned char quicc_scc3_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxNUM*CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
DEVTAB_ENTRY(quicc_smc_serial_io_scc3,
CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_NAME,
0, // Does not depend on a lower level interface
&cyg_io_serial_devio,
@@ -630,15 +627,15 @@ quicc_sxx_serial_init(struct cyg_devtab_
&eppc->pram[2].scc.pothers.smc_modem.psmc.u, // PRAM
&eppc->smc_regs[0], // Control registers
TxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE,
- ALIGN_TO_CACHELINES(&quicc_smc1_txbuf[0]),
+ &quicc_smc1_txbuf[0],
RxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE,
- ALIGN_TO_CACHELINES(&quicc_smc1_rxbuf[0]),
+ &quicc_smc1_rxbuf[0],
0xC0, // PortB mask
QUICC_CPM_SMC1
);
}
#endif
@@ -650,15 +647,15 @@ quicc_sxx_serial_init(struct cyg_devtab_
&eppc->pram[3].scc.pothers.smc_modem.psmc.u, // PRAM
&eppc->smc_regs[1], // Control registers
TxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE,
- ALIGN_TO_CACHELINES(&quicc_smc2_txbuf[0]),
+ &quicc_smc2_txbuf[0],
RxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE,
- ALIGN_TO_CACHELINES(&quicc_smc2_rxbuf[0]),
+ &quicc_smc2_rxbuf[0],
0xC00, // PortB mask
QUICC_CPM_SMC2
);
}
#endif
@@ -670,15 +667,15 @@ quicc_sxx_serial_init(struct cyg_devtab_
&eppc->pram[0].scc.pscc.u, // PRAM
&eppc->scc_regs[0], // Control registersn
TxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxNUM,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_TxSIZE,
- ALIGN_TO_CACHELINES(&quicc_scc1_txbuf[0]),
+ &quicc_scc1_txbuf[0],
RxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxNUM,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC1_RxSIZE,
- ALIGN_TO_CACHELINES(&quicc_scc1_rxbuf[0]),
+ &quicc_scc1_rxbuf[0],
0x0003, // PortA mask
0x1000, // PortB mask
0x0800, // PortC mask
QUICC_CPM_SCC1
);
@@ -692,15 +689,15 @@ quicc_sxx_serial_init(struct cyg_devtab_
&eppc->pram[1].scc.pscc.u, // PRAM
&eppc->scc_regs[1], // Control registersn
TxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxNUM,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_TxSIZE,
- ALIGN_TO_CACHELINES(&quicc_scc2_txbuf[0]),
+ &quicc_scc2_txbuf[0],
RxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxNUM,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC2_RxSIZE,
- ALIGN_TO_CACHELINES(&quicc_scc2_rxbuf[0]),
+ &quicc_scc2_rxbuf[0],
0x000C, // PortA mask
0x2000, // PortB mask
0x0C00, // PortC mask
QUICC_CPM_SCC2
);
@@ -714,15 +711,15 @@ quicc_sxx_serial_init(struct cyg_devtab_
&eppc->pram[2].scc.pscc.u, // PRAM
&eppc->scc_regs[2], // Control registersn
TxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxNUM,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_TxSIZE,
- ALIGN_TO_CACHELINES(&quicc_scc3_txbuf[0]),
+ &quicc_scc3_txbuf[0],
RxBD,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxNUM,
CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SCC3_RxSIZE,
- ALIGN_TO_CACHELINES(&quicc_scc3_rxbuf[0]),
+ &quicc_scc3_rxbuf[0],
0x0000, // PortA mask
0x00C0, // PortB mask
0x0000, // PortC mask
QUICC_CPM_SCC3
);
--
------------------------------------------------------------
Gary Thomas |
MLB Associates | Consulting for the
+1 (970) 229-1963 | Embedded world
http://www.mlbassoc.com/ |
email: <gary at mlbassoc dot com> |
gpg: http://www.chez-thomas.org/gary/gpg_key.asc
------------------------------------------------------------