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AT91 peripheral register additions/fixes


       Hi,

Below is a patch to add some missing AT91 peripheral register defines,
and also to fix a couple of typos.


Best wishes,
   --Daniel

Index: hal/arm/at91/var/current/ChangeLog
===================================================================
RCS file: /home/dne/cvsroot/redhat/ecos/packages/hal/arm/at91/var/current/ChangeLog,v
retrieving revision 1.1.1.2
retrieving revision 1.5
diff -u -5 -p -r1.1.1.2 -r1.5
--- hal/arm/at91/var/current/ChangeLog	2003/05/16 09:09:54	1.1.1.2
+++ hal/arm/at91/var/current/ChangeLog	2003/05/27 13:59:59	1.5
@@ -1,5 +1,15 @@
+2003-05-27  Daniel Néri  <daniel.neri@sigicom.se>
+
+	* include/var_io.h: Add missing USART register defines.
+	Fix cut'n'paste typos in AT91_PS defines.
+
+2003-05-16  Daniel Néri  <daniel.neri@sigicom.se>
+
+	* include/var_io.h: Add missing PIO register defines. Add
+	CPU clock disable command bit.
+
 2003-05-15  Nick Garnett  <nickg@balti.calivar.com>
 
 	* src/at91_misc.c (hal_delay_us): Added calculation to better
 	approximate the number of timer ticks for a given number of
 	microseconds. This code also now adjust to the actual CPU clock
Index: hal/arm/at91/var/current/include/var_io.h
===================================================================
RCS file: /home/dne/cvsroot/redhat/ecos/packages/hal/arm/at91/var/current/include/var_io.h,v
retrieving revision 1.1.1.1
retrieving revision 1.5
diff -u -5 -p -r1.1.1.1 -r1.5
--- hal/arm/at91/var/current/include/var_io.h	2003/05/14 08:47:19	1.1.1.1
+++ hal/arm/at91/var/current/include/var_io.h	2003/05/27 13:57:05	1.5
@@ -73,10 +73,11 @@
 #define AT91_US_CR_RxENAB  (1<<4)
 #define AT91_US_CR_RxDISAB (1<<5)
 #define AT91_US_CR_TxENAB  (1<<6)
 #define AT91_US_CR_TxDISAB (1<<7)
 #define AT91_US_CR_RSTATUS (1<<8)
+#define AT91_US_CR_STTTO   (1<<11)
 #define AT91_US_MR  0x04  // Mode register
 #define AT91_US_MR_CLOCK   4
 #define AT91_US_MR_CLOCK_MCK  (0<<AT91_US_MR_CLOCK)
 #define AT91_US_MR_CLOCK_MCK8 (1<<AT91_US_MR_CLOCK)
 #define AT91_US_MR_CLOCK_SCK  (2<<AT91_US_MR_CLOCK)
@@ -120,15 +121,21 @@
 #define AT91_US_IDR 0x0C  // Interrupt disable register
 #define AT91_US_IMR 0x10  // Interrupt mask register
 #define AT91_US_CSR 0x14  // Channel status register
 #define AT91_US_CSR_RxRDY 0x01 // Receive data ready
 #define AT91_US_CSR_TxRDY 0x02 // Transmit ready
+#define AT91_US_CSR_OVRE  0x20 // Overrun error
+#define AT91_US_CSR_FRAME 0x40 // Framing error
 #define AT91_US_RHR 0x18  // Receive holding register
 #define AT91_US_THR 0x1C  // Transmit holding register
 #define AT91_US_BRG 0x20  // Baud rate generator
 #define AT91_US_RTO 0x24  // Receive time out
 #define AT91_US_TTG 0x28  // Transmit timer guard
+#define AT91_US_RPR 0x30  // Receive pointer register
+#define AT91_US_RCR 0x34  // Receive counter register
+#define AT91_US_TPR 0x38  // Transmit pointer register
+#define AT91_US_TCR 0x3c  // Transmit counter register
 
 #define AT91_US_BAUD(baud) (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/(16*(baud)))
 
 //=============================================================================
 // PIO
@@ -139,13 +146,23 @@
 
 #define AT91_PIO_PER  0x00  // PIO enable
 #define AT91_PIO_PDR  0x04  // PIO disable
 #define AT91_PIO_PSR  0x08  // PIO status
 #define AT91_PIO_OER  0x10  // Output enable
+#define AT91_PIO_ODR  0x14  // Output disable
+#define AT91_PIO_OSR  0x18  // Output status
+#define AT91_PIO_IFER 0x20  // Input Filter enable
+#define AT91_PIO_IFDR 0x24  // Input Filter disable
+#define AT91_PIO_IFSR 0x28  // Input Filter status
 #define AT91_PIO_SODR 0x30  // Set out bits
 #define AT91_PIO_CODR 0x34  // Clear out bits
+#define AT91_PIO_ODSR 0x38  // Output data status
 #define AT91_PIO_PDSR 0x3C  // Pin data status
+#define AT91_PIO_IER  0x40  // Interrupt enable
+#define AT91_PIO_IDR  0x44  // Interrupt disable
+#define AT91_PIO_IMR  0x48  // Interrupt mask
+#define AT91_PIO_ISR  0x4C  // Interrupt status
 
 //=============================================================================
 // Advanced Interrupt Controller (AIC)
 
 #ifndef AT91_AIC
@@ -376,13 +393,14 @@
 #ifndef AT91_PS
 #define AT91_PS         0xFFFF4000
 #endif
 
 #define AT91_PS_CR        0x000    // Control
+#define AT91_PS_CR_CPU    (1<<0)   // Disable CPU clock
 #define AT91_PS_PCER      0x004    // Peripheral clock enable
-#define AT91_PS_PCDR      0x004    // Peripheral clock disable
-#define AT91_PS_PCSR      0x004    // Peripheral clock status
+#define AT91_PS_PCDR      0x008    // Peripheral clock disable
+#define AT91_PS_PCSR      0x00c    // Peripheral clock status
 
 #elif defined(CYGHWR_HAL_ARM_AT91_M42800A) || \
       defined(CYGHWR_HAL_ARM_AT91_M55800A)
 
 // (Advanced) Power Management

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