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Rattler - Adding PCI
- From: Gary Thomas <gary at mlbassoc dot com>
- To: eCos patches <ecos-patches at sources dot redhat dot com>
- Date: 26 Aug 2003 11:07:01 -0600
- Subject: Rattler - Adding PCI
- Organization: MLB Associates
Minimal setup since this card is just a PCI agent.
--
Gary Thomas <gary@mlbassoc.com>
MLB Associates
Index: hal/powerpc/mpc8xxx/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xxx/current/ChangeLog,v
retrieving revision 1.1
diff -u -5 -p -r1.1 ChangeLog
--- hal/powerpc/mpc8xxx/current/ChangeLog 19 Aug 2003 17:29:47 -0000 1.1
+++ hal/powerpc/mpc8xxx/current/ChangeLog 26 Aug 2003 17:00:28 -0000
@@ -1,5 +1,9 @@
+2003-08-26 Gary Thomas <gary@mlbassoc.com>
+
+ * include/mpc8xxx.h: Flesh out PCI definitions.
+
2003-08-19 Gary Thomas <gary@mlbassoc.com>
* src/variant.S:
* src/var_misc.c:
* src/var_intr.c:
Index: hal/powerpc/mpc8xxx/current/include/mpc8xxx.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/mpc8xxx/current/include/mpc8xxx.h,v
retrieving revision 1.1
diff -u -5 -p -r1.1 mpc8xxx.h
--- hal/powerpc/mpc8xxx/current/include/mpc8xxx.h 19 Aug 2003 17:29:48 -0000 1.1
+++ hal/powerpc/mpc8xxx/current/include/mpc8xxx.h 26 Aug 2003 15:10:12 -0000
@@ -897,15 +897,145 @@ typedef _Packed struct
volatile CYG_WORD tstmlr;
volatile CYG_WORD16 tster;
volatile CYG_BYTE reserved34[0x156]; /* Reserved area */
/* pci, part 2 */
- volatile CYG_WORD pci_pci; /* PCI Configuration space */
- volatile CYG_BYTE reserved35[0x7fc]; /* Reserved area */
+ volatile CYG_WORD pci_pci; /* PCI Configuration space - offset 0x10400 */
+ volatile CYG_BYTE reserved_pci404[0x10430-0x10404];
+ volatile CYG_WORD pci_omisr; /* Outbound interrupt status */
+ volatile CYG_WORD pci_omimr; /* Outbound interrupt mask */
+ volatile CYG_WORD reserved_pci438;
+ volatile CYG_WORD reserved_pci43C;
+ volatile CYG_WORD pci_ifqpr; /* Inbound FIFO queue */
+ volatile CYG_WORD pci_ofqpr; /* Outbound FIFO queue */
+ volatile CYG_WORD reserved_pci448;
+ volatile CYG_WORD reserved_pci44C;
+ volatile CYG_WORD pci_imr; /* Inbound message register #0 */
+ volatile CYG_WORD pci_imr1; /* Inbound message register #1 */
+ volatile CYG_WORD pci_omr0; /* Outbound message register #0 */
+ volatile CYG_WORD pci_omr1; /* Outbound message register #1 */
+ volatile CYG_WORD pci_odr; /* Outbound doorbell */
+ volatile CYG_WORD reserved_pci464;
+ volatile CYG_WORD pci_idr; /* Inbound doorbell */
+ volatile CYG_BYTE reserved_pci46C[0x10480-0x1046C];
+ volatile CYG_WORD pci_imisr; /* Inbound message interrupt status */
+ volatile CYG_WORD pci_imimr; /* Inbound message interrupt mask */
+ volatile CYG_BYTE reserved_pci488[0x104A0-0x10488];
+ volatile CYG_WORD pci_ifhpr; /* Inbound free FIFO head */
+ volatile CYG_WORD reserved_pci4A4;
+ volatile CYG_WORD pci_iftpr; /* Inbound free FIFO tail */
+ volatile CYG_WORD reserved_pci4AC;
+ volatile CYG_WORD pci_iphpr; /* Inbound post FIFO head */
+ volatile CYG_WORD reserved_pci4B4;
+ volatile CYG_WORD pci_iptpr; /* Inbound post FIFO tail */
+ volatile CYG_WORD reserved_pci4BC;
+ volatile CYG_WORD pci_ofhpr; /* Outbound free FIFO head */
+ volatile CYG_WORD reserved_pci4C4;
+ volatile CYG_WORD pci_oftpr; /* Outbound free FIFO tail */
+ volatile CYG_WORD reserved_pci4CC;
+ volatile CYG_WORD pci_ophpr; /* Outbound post FIFO head */
+ volatile CYG_WORD reserved_pci4D4;
+ volatile CYG_WORD pci_optpr; /* Outbound post FIFO tail */
+ volatile CYG_WORD reserved_pci4DC;
+ volatile CYG_WORD reserved_pci4E0;
+ volatile CYG_WORD pci_mucr; /* Message unit control */
+ volatile CYG_BYTE reserved_pci4E8[0x104F0-0x104E8];
+ volatile CYG_WORD pci_qbar; /* Queue base address */
+ volatile CYG_BYTE reserved_pci4F4[0x10500-0x104F4];
+ volatile CYG_WORD pci_dmamr0; /* DMA #0 - mode */
+ volatile CYG_WORD pci_dmasr0; /* DMA #0 - status */
+ volatile CYG_WORD pci_dmacdar0; /* DMA #0 - current descriptor address */
+ volatile CYG_WORD reserved_pci50C;
+ volatile CYG_WORD pci_dmasar0; /* DMA #0 - source address */
+ volatile CYG_WORD reserved_pci514;
+ volatile CYG_WORD pci_dmadar0; /* DMA #0 - destination address */
+ volatile CYG_WORD reserved_pci51C;
+ volatile CYG_WORD pci_dmabcr0; /* DMA #0 - byte count */
+ volatile CYG_WORD pci_dmandar0; /* DMA #0 - next descriptor */
+ volatile CYG_BYTE reserved_pci528[0x10580-0x10528];
+ volatile CYG_WORD pci_dmamr1; /* DMA #1 - mode */
+ volatile CYG_WORD pci_dmasr1; /* DMA #1 - status */
+ volatile CYG_WORD pci_dmacdar1; /* DMA #1 - current descriptor address */
+ volatile CYG_WORD reserved_pci58C;
+ volatile CYG_WORD pci_dmasar1; /* DMA #1 - source address */
+ volatile CYG_WORD reserved_pci594;
+ volatile CYG_WORD pci_dmadar1; /* DMA #1 - destination address */
+ volatile CYG_WORD reserved_pci59C;
+ volatile CYG_WORD pci_dmabcr1; /* DMA #1 - byte count */
+ volatile CYG_WORD pci_dmandar1; /* DMA #1 - next descriptor */
+ volatile CYG_BYTE reserved_pci5A8[0x10600-0x105A8];
+ volatile CYG_WORD pci_dmamr2; /* DMA #2 - mode */
+ volatile CYG_WORD pci_dmasr2; /* DMA #2 - status */
+ volatile CYG_WORD pci_dmacdar2; /* DMA #2 - current descriptor address */
+ volatile CYG_WORD reserved_pci60C;
+ volatile CYG_WORD pci_dmasar2; /* DMA #2 - source address */
+ volatile CYG_WORD reserved_pci614;
+ volatile CYG_WORD pci_dmadar2; /* DMA #2 - destination address */
+ volatile CYG_WORD reserved_pci61C;
+ volatile CYG_WORD pci_dmabcr2; /* DMA #2 - byte count */
+ volatile CYG_WORD pci_dmandar2; /* DMA #2 - next descriptor */
+ volatile CYG_BYTE reserved_pci628[0x10680-0x10628];
+ volatile CYG_WORD pci_dmamr3; /* DMA #3 - mode */
+ volatile CYG_WORD pci_dmasr3; /* DMA #3 - status */
+ volatile CYG_WORD pci_dmacdar3; /* DMA #3 - current descriptor address */
+ volatile CYG_WORD reserved_pci68C;
+ volatile CYG_WORD pci_dmasar3; /* DMA #3 - source address */
+ volatile CYG_WORD reserved_pci694;
+ volatile CYG_WORD pci_dmadar3; /* DMA #3 - destination address */
+ volatile CYG_WORD reserved_pci69C;
+ volatile CYG_WORD pci_dmabcr3; /* DMA #3 - byte count */
+ volatile CYG_WORD pci_dmandar3; /* DMA #3 - next descriptor */
+ volatile CYG_BYTE reserved_pci6A8[0x10800-0x106A8];
+ volatile CYG_WORD pci_potar0; /* PCI outbound translation address #0 */
+ volatile CYG_WORD reserved_pci804;
+ volatile CYG_WORD pci_potbar0; /* PCI outbound base address #0 */
+ volatile CYG_WORD reserved_pci80C;
+ volatile CYG_WORD pci_pocmr0; /* PCI outbound comparison mask #0 */
+ volatile CYG_WORD reserved_pci814;
+ volatile CYG_WORD pci_potar1; /* PCI outbound translation address #1 */
+ volatile CYG_WORD reserved_pci81C;
+ volatile CYG_WORD pci_potbar1; /* PCI outbound base address #1 */
+ volatile CYG_WORD reserved_pci824;
+ volatile CYG_WORD pci_pocmr1; /* PCI outbound comparison mask #1 */
+ volatile CYG_WORD reserved_pci82C;
+ volatile CYG_WORD pci_potar2; /* PCI outbound translation address #2 */
+ volatile CYG_WORD reserved_pci834;
+ volatile CYG_WORD pci_potbar2; /* PCI outbound base address #2 */
+ volatile CYG_WORD reserved_pci83C;
+ volatile CYG_WORD pci_pocmr2; /* PCI outbound comparison mask #2 */
+ volatile CYG_BYTE reserved_pci844[0x10878-0x10844];
+ volatile CYG_WORD pci_ptcr; /* Discard timer control */
+ volatile CYG_WORD pci_gpcr; /* General purpose control */
+ volatile CYG_WORD pci_gcr; /* PCI general control */
+ volatile CYG_WORD pci_esr; /* Error status */
+ volatile CYG_WORD pci_emr; /* Error mask */
+ volatile CYG_WORD pci_ecr; /* Error control */
+ volatile CYG_WORD pci_eacr; /* Error address capture */
+ volatile CYG_WORD reserved_pci894;
+ volatile CYG_WORD pci_edcr; /* Error data capture */
+ volatile CYG_WORD reserved_pci89C;
+ volatile CYG_WORD pci_eccr; /* Error control */
+ volatile CYG_BYTE reserved_pci8D0[0x108D0-0x108A4];
+ volatile CYG_WORD pci_pitar1; /* Inbound address translation #1 */
+ volatile CYG_WORD reserved_pci8D8;
+ volatile CYG_WORD pci_pibar1; /* Inbound address base #1 */
+ volatile CYG_WORD reserved_pci8E0;
+ volatile CYG_WORD pci_picmr1; /* Inbound comparison mask #1 */
+ volatile CYG_WORD reserved_pci8E8;
+ volatile CYG_WORD pci_pitar0; /* Inbound address translation #0 */
+ volatile CYG_WORD reserved_pci8F0;
+ volatile CYG_WORD pci_pibar0; /* Inbound address base #0 */
+ volatile CYG_WORD reserved_pci8F8;
+ volatile CYG_WORD pci_picmr0; /* Inbound comparison mask #0 */
+ volatile CYG_WORD reserved_pci900;
+ volatile CYG_WORD pci_cfg_addr; /* Indirect access to PCI config space - address ptr */
+ volatile CYG_WORD pci_cfg_data; /* Indirect access to PCI config space - data */
+ volatile CYG_WORD pci_int_ack; /* Used to acknowledge PCI interrupts */
+ volatile CYG_BYTE reserved_pci0C00[0x10C00-0x1090C];
/* ic */
- volatile CYG_WORD16 ic_sicr; /* Interrupt Configuration Register */
+ volatile CYG_WORD16 ic_sicr; /* Interrupt Configuration Register - offset 0x10C00 */
volatile CYG_BYTE reserved36[0x2]; /* Reserved area */
volatile CYG_BYTE ic_sivec; /* CP Interrupt Vector Register */
volatile CYG_BYTE reserved36a[0x3]; /* Reserved area */
volatile CYG_WORD ic_sipnr_h; /* Interrupt Pending Register (HIGH) */
volatile CYG_WORD ic_sipnr_l; /* Interrupt Pending Register (LOW) */
Index: hal/powerpc/rattler/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/rattler/current/ChangeLog,v
retrieving revision 1.1
diff -u -5 -p -r1.1 ChangeLog
--- hal/powerpc/rattler/current/ChangeLog 19 Aug 2003 17:29:48 -0000 1.1
+++ hal/powerpc/rattler/current/ChangeLog 26 Aug 2003 17:03:09 -0000
@@ -1,5 +1,10 @@
+2003-08-26 Gary Thomas <gary@mlbassoc.com>
+
+ * src/rattler.S:
+ * src/hal_aux.c: Add PCI initialization - agent mode only.
+
2003-08-19 Gary Thomas <gary@mlbassoc.com>
* src/redboot_linux_exec.c:
* src/rattler.S:
* src/hal_diag.c:
Index: hal/powerpc/rattler/current/src/hal_aux.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/rattler/current/src/hal_aux.c,v
retrieving revision 1.1
diff -u -5 -p -r1.1 hal_aux.c
--- hal/powerpc/rattler/current/src/hal_aux.c 19 Aug 2003 17:29:49 -0000 1.1
+++ hal/powerpc/rattler/current/src/hal_aux.c 26 Aug 2003 16:20:58 -0000
@@ -56,10 +56,49 @@
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/mpc8xxx.h> // For IMM structures
#include <cyg/hal/hal_if.h>
#include <cyg/hal/hal_intr.h>
+// FIXME
+
+static __inline__ unsigned long
+_le32(unsigned long val)
+{
+ return (((val & 0x000000FF) << 24) |
+ ((val & 0x0000FF00) << 8) |
+ ((val & 0x00FF0000) >> 8) |
+ ((val & 0xFF000000) >> 24));
+}
+
+static __inline__ unsigned short
+_le16(unsigned short val)
+{
+ return (((val & 0x000000FF) << 8) |
+ ((val & 0x0000FF00) >> 8));
+}
+
+#define HAL_WRITE_UINT32LE(_addr_, _val_) \
+ HAL_WRITE_UINT32(_addr_, _le32(_val_))
+#define HAL_WRITE_UINT16LE(_addr_, _val_) \
+ HAL_WRITE_UINT16(_addr_, _le16(_val_))
+#define HAL_WRITE_UINT8LE(_addr_, _val_) \
+ HAL_WRITE_UINT8(_addr_, _val_)
+#define HAL_READ_UINT32LE(_addr_, _val_) \
+ { \
+ HAL_READ_UINT32(_addr_, _val_); \
+ _val_ = _le32(_val_); \
+ }
+#define HAL_READ_UINT16LE(_addr_, _val_) \
+ { \
+ HAL_READ_UINT16(_addr_, _val_); \
+ _val_ = _le16(_val_); \
+ }
+#define HAL_READ_UINT8LE(_addr_, _val_) \
+ HAL_READ_UINT8(_addr_, _val_)
+
+// FIXME
+
// The memory map is weakly defined, allowing the application to redefine
// it if necessary. The regions defined below are the minimum requirements.
CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = {
// Mapping for the Rattler board
CYGARC_MEMDESC_CACHE( 0x00000000, 0x01000000 ), // Main memory 60x SDRAM
@@ -330,10 +369,37 @@ hal_platform_init(void)
// xx SMC2 - clock on BRG8
IMM->cpm_mux_cmxsmr = 0x11;
// Start up system I/O
hal_if_init();
+
+#ifdef CYGHWR_HAL_POWERPC_RATTLER_PCI
+ if ((IMM->clocks_sccr & 0x100) != 0) {
+ CYG_WORD16 pci_cfg;
+
+ HAL_WRITE_UINT32LE(&IMM->pci_cfg_addr, 0x80000004);
+ HAL_WRITE_UINT16LE(&IMM->pci_cfg_data, 0);
+ // Configure PCI address registers
+ IMM->pcimsk1 = 0xC0000000;
+ IMM->pcibr1 = 0x80000001;
+ IMM->pcimsk0 = 0xFF800000;
+ IMM->pcibr0 = 0x48000001;
+ IMM->pci_gpcr = 0;
+ IMM->pci_picmr1 = 0xF0FF0FE0;
+ IMM->pci_picmr0 = 0xF0FF0FE0;
+ // Now disable CFG_LOCK to free bus
+ HAL_WRITE_UINT32LE(&IMM->pci_cfg_addr, 0x80000044);
+ HAL_READ_UINT16LE(&IMM->pci_cfg_data, pci_cfg);
+ pci_cfg &= ~0x20; // Turn off CFG_LOCK
+ HAL_WRITE_UINT32LE(&IMM->pci_cfg_addr, 0x80000044);
+ HAL_WRITE_UINT16LE(&IMM->pci_cfg_data, pci_cfg);
+ HAL_WRITE_UINT32LE(&IMM->pci_cfg_addr, 0x80000044);
+ HAL_READ_UINT16LE(&IMM->pci_cfg_data, pci_cfg);
+ } else {
+ diag_printf("*** Warning: PCI not responding - SCCR: %x\n", IMM->clocks_sccr);
+ }
+#endif
}
//
// Cause the platform to reset
//
Index: hal/powerpc/rattler/current/src/rattler.S
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/powerpc/rattler/current/src/rattler.S,v
retrieving revision 1.1
diff -u -5 -p -r1.1 rattler.S
--- hal/powerpc/rattler/current/src/rattler.S 19 Aug 2003 17:29:49 -0000 1.1
+++ hal/powerpc/rattler/current/src/rattler.S 26 Aug 2003 16:49:23 -0000
@@ -101,13 +101,20 @@ hal_hardware_init:
// SC SYPCR fF010004 FFFFFFC3 SIU
// SC SWSR fF01000E 0000 SIU
lwi r3,0xFFFFFFC3
stw r3,CYGARC_REG_IMM_SYPCR(r30)
- lwi r3,0x00000001
+ lwz r3,CYGARC_REG_IMM_SCCR(r30)
+ ori r3,r3,0x00000001 // Force baud rate clock divisor = 16
stw r3,CYGARC_REG_IMM_SCCR(r30)
- lwi r3,0x0E24C000
+#ifdef CYGHWR_HAL_POWERPC_RATTLER_PCI
+ lwz r3,CYGARC_REG_IMM_SIUMCR(r30)
+ lwi r4,0x0E040000 // Set configuration bits
+ or r3,r3,r4
+#else
+ lwi r3,0x0E24C000 // Set configuration bits
+#endif
stw r3,CYGARC_REG_IMM_SIUMCR(r30)
li r3,0x0000
sth r3,CYGARC_REG_IMM_SWSR(r30)
// SC BCR fF010024 00000000 SIU