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PLL configury for LPC
- From: Jani Monoses <jani at iv dot ro>
- To: ecos-patches at ecos dot sourceware dot org
- Date: Fri, 19 Nov 2004 15:35:36 +0200
- Subject: PLL configury for LPC
Hello
this makes the clock frequency configurable.Given a fixed crystal ferquency the PLL
multiplier can be set.For the MCB2100 and the LPC2106 targets.
Jani
--- orig/packages/hal/arm/lpc2xxx/mcb2100/current/ChangeLog
+++ mod/packages/hal/arm/lpc2xxx/mcb2100/current/ChangeLog
@@ -1,5 +1,11 @@
2004-11-19 Jani Monoses <jani@iv.ro>
+ * cdl/hal_arm_lpc2xxx_mcb2100.cdl:
+ * include/hal_platform_setup.h:
+ Make PLL multiplier value configurable.
+
+2004-11-19 Jani Monoses <jani@iv.ro>
+
* include/hal_platform_setup.h:
Fix previous fix. LDR needs its operand prefixed with = not #.
--- orig/packages/hal/arm/lpc2xxx/mcb2100/current/cdl/hal_arm_lpc2xxx_mcb2100.cdl
+++ mod/packages/hal/arm/lpc2xxx/mcb2100/current/cdl/hal_arm_lpc2xxx_mcb2100.cdl
@@ -128,12 +128,23 @@
}
# Real-time clock/counter specifics
- cdl_option CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED {
+ cdl_option CYGNUM_HAL_ARM_LPC2XXX_XTAL_FREQ {
+ display "CPU clock speed"
+ flavor data
+ default_value {12000000}
+ }
+
+ cdl_option CYGNUM_HAL_ARM_LPC2XXX_PLL_MUL {
display "CPU clock speed"
flavor data
- default_value {60000000}
+ default_value {5}
}
+ cdl_option CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED {
+ display "CPU clock speed"
+ flavor data
+ calculated { CYGNUM_HAL_ARM_LPC2XXX_PLL_MUL * CYGNUM_HAL_ARM_LPC2XXX_XTAL_FREQ }
+ }
cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"
--- orig/packages/hal/arm/lpc2xxx/mcb2100/current/include/hal_platform_setup.h
+++ mod/packages/hal/arm/lpc2xxx/mcb2100/current/include/hal_platform_setup.h
@@ -53,6 +53,7 @@
//
//===========================================================================*/
+#include <pkgconf/system.h>
#include <cyg/hal/var_io.h>
//===========================================================================*/
@@ -80,9 +81,8 @@
mov r1,#1 // enable PLL
str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLCON]
- mov r1,#0x24
- // set M and P:core runs at 60MHz (5 times 12MHz xtal frequency)
- str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLCFG]
+ mov r1,#(0x20 | (CYGNUM_HAL_ARM_LPC2XXX_PLL_MUL - 1))
+ str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLCFG]
str r2,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLFEED] // update PLL registers
str r3,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLFEED]
--- orig/packages/hal/arm/lpc2xxx/p2106/current/ChangeLog
+++ mod/packages/hal/arm/lpc2xxx/p2106/current/ChangeLog
@@ -1,3 +1,9 @@
+2004-11-19 Jani Monoses <jani@iv.ro>
+
+ * cdl/hal_arm_lpc2xxx_p2106.cdl:
+ * include/hal_platform_setup.h:
+ Make PLL multiplier value configurable.
+
2004-11-15 Jani Monoses <jani@iv.ro>
* include/hal_platform_setup.h:
--- orig/packages/hal/arm/lpc2xxx/p2106/current/cdl/hal_arm_lpc2xxx_p2106.cdl
+++ mod/packages/hal/arm/lpc2xxx/p2106/current/cdl/hal_arm_lpc2xxx_p2106.cdl
@@ -123,15 +123,27 @@
description "
This option controls the baud rate used for the GDB connection."
}
-
+
# Real-time clock/counter specifics
- cdl_option CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED {
+ cdl_option CYGNUM_HAL_ARM_LPC2XXX_XTAL_FREQ {
display "CPU clock speed"
flavor data
- default_value {58982400}
+ default_value {14745600}
}
- cdl_component CYGBLD_GLOBAL_OPTIONS {
+ cdl_option CYGNUM_HAL_ARM_LPC2XXX_PLL_MUL {
+ display "CPU clock speed"
+ flavor data
+ default_value {4}
+ }
+
+ cdl_option CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED {
+ display "CPU clock speed"
+ flavor data
+ calculated { CYGNUM_HAL_ARM_LPC2XXX_PLL_MUL * CYGNUM_HAL_ARM_LPC2XXX_XTAL_FREQ }
+ }
+
+ cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"
flavor none
parent CYGPKG_NONE
--- orig/packages/hal/arm/lpc2xxx/p2106/current/include/hal_platform_setup.h
+++ mod/packages/hal/arm/lpc2xxx/p2106/current/include/hal_platform_setup.h
@@ -53,6 +53,7 @@
//
//===========================================================================*/
+#include <pkgconf/system.h>
#include <cyg/hal/var_io.h>
//===========================================================================*/
@@ -80,9 +81,7 @@
mov r1,#1 // enable PLL
str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLCON]
- mov r1,#0x23
- // set M and P:core runs at 58.9824MHz (4 times 14.7456MHz
- // xtal frequency)
+ mov r1,#(0x20 | (CYGNUM_HAL_ARM_LPC2XXX_PLL_MUL - 1))
str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLCFG]
str r2,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLFEED] // update PLL registers