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Re: [PATCH] Intel StrataFlash fix for MIPS


On Friday 14 January 2005 16:08, Mark Salter wrote:
> I don't think gcc can do anything about this. It sounds like there
> is a write buffer delaying the actual write to flash or the cpu is
> prefetching. So a HAL_WB_FLUSH() and/or a cache flush seems to be in
> order. Actually, aren't the caches off when the flash functions are
> running?
>
> I think the HAL_REORDER_BARRIER() is a hint to gcc not to reorder
> code across the barrier. I'm not sure about HAL_IO_BARRIER. Maybe
> that should do a write-buffer flush if needed.

Right, but the problem is totally unrelated to caching issues. It is
only that if the bus interface is busy (fetching instructions, for
example) when it receives a request to store a data item to some
address, the request will simply be postponed. Hence, any data transfer
(instruction fetch) currently underway will complete before the
store takes effect.

tk
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Thomas Koeller, Software Development

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