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AT91SAM7S flash wait states
- From: Andrew Lunn <andrew dot lunn at ascom dot ch>
- To: eCos Patches <ecos-patches at ecos dot sourceware dot org>
- Date: Wed, 23 Apr 2008 10:22:21 +0200
- Subject: AT91SAM7S flash wait states
Hi Folks
There is a stupid bug in the AT91SAM7S startup macros when the clock
is running faster than 60MHz. A register is left undefined and then
used for a store, resulting in a data abort. Patch attached.
Andrew
Index: hal/arm/at91/at91sam7s/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/ChangeLog,v
retrieving revision 1.12
diff -u -r1.12 ChangeLog
--- hal/arm/at91/at91sam7s/current/ChangeLog 26 Mar 2007 10:42:43 -0000 1.12
+++ hal/arm/at91/at91sam7s/current/ChangeLog 23 Apr 2008 08:17:02 -0000
@@ -1,3 +1,9 @@
+2008-04-23 Andrew Lunn <andrew.lunn@ascom.ch>
+
+ * include/hal_platform_setup.h: Fix setting the flash wait states
+ when the clock is running faster than 60MHz. r0 was undefined
+ causing a data abort.
+
2007-03-26 Andrew Lunn <andrew.lunn@ascom.ch>
* cdl/hal_arm_at91sam7s.cdl: SAM7X and SAM7XC have a CAN bus
Index: hal/arm/at91/at91sam7s/current/include/hal_platform_setup.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/include/hal_platform_setup.h,v
retrieving revision 1.2
diff -u -r1.2 hal_platform_setup.h
--- hal/arm/at91/at91sam7s/current/include/hal_platform_setup.h 28 Feb 2006 15:35:23 -0000 1.2
+++ hal/arm/at91/at91sam7s/current/include/hal_platform_setup.h 23 Apr 2008 08:17:02 -0000
@@ -59,9 +59,9 @@
// Macro to initialise the Memory Controller
.macro _flash_init
__flash_init__:
+ ldr r0,=AT91_MC
#if CYGNUM_HAL_ARM_AT91_CLOCK_SPEED > 30000000
// When the clock is running faster than 30MHz we need a wait state
- ldr r0,=AT91_MC
ldr r1,=(AT91_MC_FMR_1FWS)
str r1,[r0,#AT91_MC_FMR]
#endif