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Re: AT91SAM7S without crystal


On Fri, May 09, 2008 at 11:16:54AM +0100, James G. Smith wrote:
> Very minor tweak to support AT91SAM7S boards that do not use a crystal  
> to provide the main clock along with a new CDL option to select the  
> feature (defaults to CRYSTAL). In reality the wait loop after the  
> CKGR_MOR setting using OSCBYPASS is not needed since the status bit is  
> forced in such a configuration.
>
> Diff against the CVS tree as of 11:00 20080509.
>
> -- Jamie
>
> P.S. Also tweaked the flash wait-state setting code to avoid unnecessary  
> instructions when clocks greater than 60MHz used since I spotted that  
> when adding the clock setup change.

Hi Jamie

Thanks for the patch.

The crystal/clock signal part is O.K. 

The wait state code i found not very readable, the arrangement of the
#ifdef's. So i modified it a different way. I don't have access to my
AT91SAM7X-EK, so i've not been able to test this. However i did
disassemble it and it looked O.K. 

In future patches please include a ChangeLog entry.

Also please generate your patches relative to the packages
directory. It makes it easier to apply the patch without having to
find to correct level in the tree to apply it to.

     Thanks
        Andrew
Index: hal/arm/at91/at91sam7s/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/ChangeLog,v
retrieving revision 1.14
diff -u -r1.14 ChangeLog
--- hal/arm/at91/at91sam7s/current/ChangeLog	1 May 2008 10:50:26 -0000	1.14
+++ hal/arm/at91/at91sam7s/current/ChangeLog	11 May 2008 12:57:07 -0000
@@ -1,3 +1,11 @@
+2008-05-11  James G. Smith <jsmith@rallysmith.co.uk
+            Andrew Lunn  <andrew@lunn.ch>
+
+	* cdl/hal_arm_at91sam7s.cdl: CDL for crystal vs clock signal.
+	* include/hal_platform_setup.h: Rework flash wait states to remove
+	redundant code when running at > 60MHz. Support clock signal input
+	when starting the main clock.
+
 2008-04-30  John Eigelaar  <jeigelaar@mweb.co.za>
 
 	* include/pkgconf/mlt_arm_at91sam7x512_rom.{h|ldi}: Added the 
Index: hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl,v
retrieving revision 1.8
diff -u -r1.8 hal_arm_at91sam7s.cdl
--- hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl	1 May 2008 10:50:27 -0000	1.8
+++ hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl	11 May 2008 12:57:08 -0000
@@ -220,10 +220,20 @@
     cdl_option CYGNUM_HAL_ARM_AT91_CLOCK_OSC_MAIN {
         display       "Main oscillator frequency"
         flavor        data
-        legal_values { 3000000 to 20000000} 
+        legal_values  { 3000000 to 20000000} 
         default_value { 18432000 }
         description   "
-            What frequency of crystal is clocking the device."
+            The frequency of the clock input, be it a crystal or a clock 
+            signal"
+    }
+
+    cdl_option CYGNUM_HAL_ARM_AT91_CLOCK_TYPE {
+        display       "Type of main frequency input"
+        flavor        data
+        default_value { "CRYSTAL" }
+        legal_values  { "CRYSTAL" "EXTCLOCK" } 
+        description   "
+            Whether a crystal or a XIN input clock is clocking the device."
     }
 
     cdl_option CYGNUM_HAL_ARM_AT91_PLL_DIVIDER {
Index: hal/arm/at91/at91sam7s/current/include/hal_platform_setup.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/include/hal_platform_setup.h,v
retrieving revision 1.3
diff -u -r1.3 hal_platform_setup.h
--- hal/arm/at91/at91sam7s/current/include/hal_platform_setup.h	23 Apr 2008 08:17:44 -0000	1.3
+++ hal/arm/at91/at91sam7s/current/include/hal_platform_setup.h	11 May 2008 12:57:08 -0000
@@ -60,15 +60,19 @@
         .macro _flash_init
 __flash_init__:
         ldr     r0,=AT91_MC
-#if CYGNUM_HAL_ARM_AT91_CLOCK_SPEED > 30000000
+#if CYGNUM_HAL_ARM_AT91_CLOCK_SPEED > 60000000
+        // When the clock is running faster than 60MHz we need two wait states
+        ldr     r1,=(AT91_MC_FMR_2FWS)
+#else 
+# if CYGNUM_HAL_ARM_AT91_CLOCK_SPEED > 30000000
         // When the clock is running faster than 30MHz we need a wait state
         ldr     r1,=(AT91_MC_FMR_1FWS)
-        str     r1,[r0,#AT91_MC_FMR]
+# else
+        // We have a slow clock, no extra wait states are needed
+        ldr     r1,=AT91_MC_FMR_0FWS
+# endif
 #endif
-#if CYGNUM_HAL_ARM_AT91_CLOCK_SPEED > 60000000
-        ldr     r1,=(AT91_MC_FMR_2FWS)
         str     r1,[r0,#AT91_MC_FMR]
-#endif
         .endm
 
 // Macro to start the main clock.
@@ -79,7 +83,11 @@
         ldr     r1,=(AT91_PMC_MCKR_PRES_CLK|AT91_PMC_MCKR_SLOW_CLK)
         str     r1,[r0,#AT91_PMC_MCKR]
 	// startup time
+#if defined(CYGNUM_HAL_ARM_AT91_CLOCK_TYPE_EXTCLOCK)
+        ldr     r1,=(AT91_PMC_MOR_OSCBYPASS)
+#else
         ldr     r1,=(AT91_PMC_MOR_OSCCOUNT(6)|AT91_PMC_MOR_MOSCEN)
+#endif
         str     r1,[r0,#AT91_PMC_MOR]
 
         // Wait for oscilator start timeout

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