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mailing list for the eCos project.
Re: AT91 HAL, AT91 USB, AT91 flash and USB-serial patches
- From: Andrew Lunn <andrew at lunn dot ch>
- To: G?bor T?r?k <tgabor84 at gmail dot com>
- Cc: ecos-patches at ecos dot sourceware dot org
- Date: Mon, 3 Nov 2008 14:55:29 +0100
- Subject: Re: AT91 HAL, AT91 USB, AT91 flash and USB-serial patches
- References: <30c102240810211232u9bdd2bcr984c78eef606ae2f@mail.gmail.com>
On Tue, Oct 21, 2008 at 09:32:45PM +0200, G?bor T?r?k wrote:
> These patches mostly contain modifications needed to run eCos on Atmel
> AT91SAM7SE.
Hi Gabor
Thanks for these changes. I reformated some of them and added
ChangeLog entries. Attached is the patch.
Andrew
Index: devs/usb/at91/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/usb/at91/current/ChangeLog,v
retrieving revision 1.5
diff -u -r1.5 ChangeLog
--- devs/usb/at91/current/ChangeLog 20 Nov 2007 11:00:06 -0000 1.5
+++ devs/usb/at91/current/ChangeLog 3 Nov 2008 08:38:37 -0000
@@ -1,3 +1,11 @@
+2008-11-03 Gabor Toeroek <tgabor84@gmail.com>
+
+ * cdl/usbs_at91.cdl:
+ * include/usbs_at91.h:
+ * src/usbs_at91.c:
+ * src/usbs_at91_data.c: Support for SAM7SE which has an internal
+ pullup. Added extra endpoints for those chips that have them.
+
2007-11-20 Andrew Lunn <andrew.lunn@ascom.ch>
* cdl/usbs_at91.cdl: Fixed typos in
Index: devs/usb/at91/current/cdl/usbs_at91.cdl
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/usb/at91/current/cdl/usbs_at91.cdl,v
retrieving revision 1.4
diff -u -r1.4 usbs_at91.cdl
--- devs/usb/at91/current/cdl/usbs_at91.cdl 20 Nov 2007 11:00:06 -0000 1.4
+++ devs/usb/at91/current/cdl/usbs_at91.cdl 3 Nov 2008 08:38:38 -0000
@@ -93,6 +93,17 @@
Enable support for endpoint 0. If this support is disabled
then the entire USB port is unusable."
+ cdl_option CYGDAT_DEVS_USB_AT91_GPIO_SET_PULLUP_INTERNAL {
+ display "The chip has internal pullup"
+ flavor bool
+ calculated { CYGHWR_HAL_ARM_AT91SAM7SE }
+ requires { CYGDAT_DEVS_USB_AT91_GPIO_SET_PULLUP_PIN == "NONE" }
+ description "
+ The chip has an internal pullup resistor;
+ the use of this pullup is mandatory (?), so there
+ should be no external pullup resistor."
+ }
+
cdl_option CYGDAT_DEVS_USB_AT91_GPIO_SET_PULLUP_PIN {
display "PIO-Pin who controls the pullup resistor"
flavor data
@@ -105,6 +116,7 @@
cdl_option CYGNUM_DEVS_USB_AT91_GPIO_SET_PULLUP_INVERTED {
display "Has the signal to be inverted?"
+ active_if {CYGDAT_DEVS_USB_AT91_GPIO_SET_PULLUP_PIN != "NONE"}
flavor bool
default_value 1
description "
Index: devs/usb/at91/current/include/usbs_at91.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/usb/at91/current/include/usbs_at91.h,v
retrieving revision 1.1
diff -u -r1.1 usbs_at91.h
--- devs/usb/at91/current/include/usbs_at91.h 7 May 2006 15:10:56 -0000 1.1
+++ devs/usb/at91/current/include/usbs_at91.h 3 Nov 2008 08:38:38 -0000
@@ -50,13 +50,31 @@
#include <cyg/io/usb/usbs.h>
#include <pkgconf/devs_usb_at91.h>
+#include <pkgconf/system.h>
+#ifdef CYGPKG_HAL_ARM_AT91SAM7
+#include <pkgconf/hal_arm_at91sam7.h>
+#endif
+#if defined(CYGHWR_HAL_ARM_AT91SAM7SE)
+#define AT91_USB_ENDPOINTS 8
+#elif defined(CYGHWR_HAL_ARM_AT91SAM7X)
+#define AT91_USB_ENDPOINTS 6
+#else
#define AT91_USB_ENDPOINTS 4
+#endif
extern usbs_control_endpoint usbs_at91_ep0;
extern usbs_rx_endpoint usbs_at91_ep1;
extern usbs_rx_endpoint usbs_at91_ep2;
extern usbs_rx_endpoint usbs_at91_ep3;
+#if (AT91_USB_ENDPOINTS > 4)
+extern usbs_rx_endpoint usbs_at91_ep4;
+extern usbs_rx_endpoint usbs_at91_ep5;
+#if (AT91_USB_ENDPOINTS > 6)
+extern usbs_rx_endpoint usbs_at91_ep6;
+extern usbs_rx_endpoint usbs_at91_ep7;
+#endif
+#endif
extern void usbs_at91_endpoint_init(usbs_rx_endpoint * pep,
cyg_uint8 endpoint_type, cyg_bool enable);
Index: devs/usb/at91/current/src/usbs_at91.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/usb/at91/current/src/usbs_at91.c,v
retrieving revision 1.4
diff -u -r1.4 usbs_at91.c
--- devs/usb/at91/current/src/usbs_at91.c 20 Nov 2007 11:00:06 -0000 1.4
+++ devs/usb/at91/current/src/usbs_at91.c 3 Nov 2008 08:38:39 -0000
@@ -49,11 +49,13 @@
//####DESCRIPTIONEND####
//==========================================================================
+#include <pkgconf/system.h>
#include <pkgconf/devs_usb_at91.h>
#include <cyg/io/usb/usb.h>
#include <cyg/io/usb/usbs.h>
#include <cyg/io/usb/usbs_at91.h>
+#include CYGBLD_HAL_PLATFORM_H
#include <cyg/hal/hal_io.h>
#include <cyg/hal/drv_api.h>
#include <cyg/hal/hal_io.h>
@@ -82,39 +84,132 @@
#define pCSRn(N) (pCSR0 + (N * 4))
#define pFDRn(N) (pFDR0 + (N * 4))
+#if (AT91_USB_ENDPOINTS == 8)
+#define AT91_UDP_ALLOWED_IRQs \
+ (AT91_UDP_WAKEUP | AT91_UDP_ENDBUSRES | AT91_UDP_EXTRSM | \
+ AT91_UDP_RXRSM | AT91_UDP_RXSUSP | AT91_UDP_EPINT0 | \
+ AT91_UDP_EPINT1 | AT91_UDP_EPINT2 | AT91_UDP_EPINT3 | \
+ AT91_UDP_EPINT4 | AT91_UDP_EPINT5 | \
+ AT91_UDP_EPINT6 | AT91_UDP_EPINT7 )
+#elif (AT91_USB_ENDPOINTS == 6)
+#define AT91_UDP_ALLOWED_IRQs \
+ (AT91_UDP_WAKEUP | AT91_UDP_ENDBUSRES | AT91_UDP_EXTRSM | \
+ AT91_UDP_RXRSM | AT91_UDP_RXSUSP | AT91_UDP_EPINT0 | \
+ AT91_UDP_EPINT1 | AT91_UDP_EPINT2 | AT91_UDP_EPINT3 | \
+ AT91_UDP_EPINT4 | AT91_UDP_EPINT5 )
+#elif (AT91_USB_ENDPOINTS == 4)
#define AT91_UDP_ALLOWED_IRQs \
(AT91_UDP_WAKEUP | AT91_UDP_ENDBUSRES | AT91_UDP_EXTRSM | \
AT91_UDP_RXRSM | AT91_UDP_RXSUSP | AT91_UDP_EPINT0 | \
AT91_UDP_EPINT1 | AT91_UDP_EPINT2 | AT91_UDP_EPINT3)
+#endif
#define THERE_IS_A_NEW_PACKET_IN_THE_UDP 0xffff
// Fifo size for each end point.
+#if defined(CYGHWR_HAL_ARM_AT91SAM7SE)
static const cyg_uint16 usbs_at91_endpoint_fifo_size[AT91_USB_ENDPOINTS] = {
8,
64,
64,
64,
+ 512,
+ 512,
+ 64,
+ 64
};
+#elif defined(CYGHWR_HAL_ARM_AT91SAM7X)
+static const cyg_uint16 usbs_at91_endpoint_fifo_size[AT91_USB_ENDPOINTS] = {
+ 8,
+ 64,
+ 64,
+ 64,
+ 256,
+ 256
+};
+#else
+static const cyg_uint16 usbs_at91_endpoint_fifo_size[AT91_USB_ENDPOINTS] = {
+ 8,
+ 64,
+ 64,
+ 64,
+};
+#endif
// Does an endpoint support ping pong buffering?
+#if defined(CYGHWR_HAL_ARM_AT91SAM7SE)
+static const bool usbs_at91_endpoint_pingpong[AT91_USB_ENDPOINTS] = {
+ false,
+ true,
+ true,
+ false,
+ true,
+ true,
+ true,
+ true
+};
+#elif defined(CYGHWR_HAL_ARM_AT91SAM7X)
+static const bool usbs_at91_endpoint_pingpong[AT91_USB_ENDPOINTS] = {
+ false,
+ true,
+ true,
+ false,
+ true,
+ true
+};
+#else
static const bool usbs_at91_endpoint_pingpong[AT91_USB_ENDPOINTS] = {
false,
true,
true,
false
};
+#endif
static cyg_uint8 *usbs_at91_endpoint_pbegin[AT91_USB_ENDPOINTS] =
+#if (AT91_USB_ENDPOINTS == 8)
+ { 0, 0, 0, 0, 0, 0, 0, 0 };
+#elif (AT91_USB_ENDPOINTS == 6)
+ { 0, 0, 0, 0, 0, 0 };
+#else
{ 0, 0, 0, 0 };
+#endif
+
static cyg_uint8 *usbs_at91_endpoint_pend[AT91_USB_ENDPOINTS] =
+#if (AT91_USB_ENDPOINTS == 8)
+ { 0, 0, 0, 0, 0, 0, 0, 0 };
+#elif (AT91_USB_ENDPOINTS == 6)
+ { 0, 0, 0, 0, 0, 0 };
+#else
{ 0, 0 ,0, 0 };
+#endif
+
static bool usbs_at91_endpoint_bank1[AT91_USB_ENDPOINTS] =
+#if (AT91_USB_ENDPOINTS == 8)
+ { false, false, false, false, false, false, false, false };
+#elif (AT91_USB_ENDPOINTS == 6)
+ { false, false, false, false, false, false };
+#else
{ false, false, false, false };
+#endif
+
static cyg_uint16 usbs_at91_endpoint_bytes_in_fifo[AT91_USB_ENDPOINTS] =
+#if (AT91_USB_ENDPOINTS == 8)
+ { 0, 0, 0, 0, 0, 0, 0, 0 };
+#elif (AT91_USB_ENDPOINTS == 6)
+ { 0, 0, 0, 0, 0, 0 };
+#else
{ 0, 0, 0, 0 };
+#endif
+
static cyg_uint16 usbs_at91_endpoint_bytes_received[AT91_USB_ENDPOINTS] =
{ THERE_IS_A_NEW_PACKET_IN_THE_UDP, THERE_IS_A_NEW_PACKET_IN_THE_UDP,
+#if (AT91_USB_ENDPOINTS > 4)
+ THERE_IS_A_NEW_PACKET_IN_THE_UDP, THERE_IS_A_NEW_PACKET_IN_THE_UDP,
+#if (AT91_USB_ENDPOINTS > 6)
+ THERE_IS_A_NEW_PACKET_IN_THE_UDP, THERE_IS_A_NEW_PACKET_IN_THE_UDP,
+#endif
+#endif
THERE_IS_A_NEW_PACKET_IN_THE_UDP, THERE_IS_A_NEW_PACKET_IN_THE_UDP};
static cyg_interrupt usbs_at91_intr_data;
@@ -196,6 +291,58 @@
halted: 0,
};
+#if (AT91_USB_ENDPOINTS > 4)
+// Endpoint 4 Receive control structure
+usbs_rx_endpoint usbs_at91_ep4 = {
+ start_rx_fn: usbs_at91_endpoint_start,
+ set_halted_fn: usbs_at91_endpoint_set_halted,
+ complete_fn: (void (*)(void *, int)) 0,
+ complete_data: (void *) 0,
+ buffer: (unsigned char *) 0,
+ buffer_size: 0,
+ halted: 0,
+};
+#endif
+
+#if (AT91_USB_ENDPOINTS > 5)
+// Endpoint 5 Receive control structure
+usbs_rx_endpoint usbs_at91_ep5 = {
+ start_rx_fn: usbs_at91_endpoint_start,
+ set_halted_fn: usbs_at91_endpoint_set_halted,
+ complete_fn: (void (*)(void *, int)) 0,
+ complete_data: (void *) 0,
+ buffer: (unsigned char *) 0,
+ buffer_size: 0,
+ halted: 0,
+};
+#endif
+
+#if (AT91_USB_ENDPOINTS > 6)
+// Endpoint 6 Receive control structure
+usbs_rx_endpoint usbs_at91_ep6 = {
+ start_rx_fn: usbs_at91_endpoint_start,
+ set_halted_fn: usbs_at91_endpoint_set_halted,
+ complete_fn: (void (*)(void *, int)) 0,
+ complete_data: (void *) 0,
+ buffer: (unsigned char *) 0,
+ buffer_size: 0,
+ halted: 0,
+};
+#endif
+
+#if (AT91_USB_ENDPOINTS > 7)
+// Endpoint 7 Receive control structure
+usbs_rx_endpoint usbs_at91_ep7 = {
+ start_rx_fn: usbs_at91_endpoint_start,
+ set_halted_fn: usbs_at91_endpoint_set_halted,
+ complete_fn: (void (*)(void *, int)) 0,
+ complete_data: (void *) 0,
+ buffer: (unsigned char *) 0,
+ buffer_size: 0,
+ halted: 0,
+};
+#endif
+
// Array of end points. Used for translating end point pointer to an
// end point number
static const void *usbs_at91_endpoints[AT91_USB_ENDPOINTS] = {
@@ -203,6 +350,12 @@
(void *) &usbs_at91_ep1,
(void *) &usbs_at91_ep2,
(void *) &usbs_at91_ep3
+#if (AT91_USB_ENDPOINTS > 4)
+ ,(void *) &usbs_at91_ep4, (void *) &usbs_at91_ep5
+#if (AT91_USB_ENDPOINTS > 6)
+ ,(void *) &usbs_at91_ep6, (void *) &usbs_at91_ep7
+#endif
+#endif
};
// Convert an endpoint pointer to an endpoint number, using the array
@@ -276,6 +429,16 @@
static void
usbs_at91_set_pullup (bool set)
{
+#ifdef CYGDAT_DEVS_USB_AT91_GPIO_SET_PULLUP_INTERNAL
+ cyg_uint32 txvc;
+ HAL_READ_UINT32(AT91_UDP + AT91_UDP_TXVC, buf);
+ if (set) {
+ txvc |= AT91_UDP_TXVC_PUON;
+ } else {
+ txvc &= ~AT91_UDP_TXVC_PUON;
+ }
+ HAL_WRITE_UINT32(AT91_UDP + AT91_UDP_TXVC, txvc);
+#endif // CYGDAT_DEVS_USB_AT91_GPIO_SET_PULLUP_INTERNAL
#ifndef CYGDAT_DEVS_USB_AT91_GPIO_SET_PULLUP_PIN_NONE
if (
@@ -466,13 +629,9 @@
}
static void
-usbs_at91_handle_reset (void)
+usbs_at91_reset_device (void)
{
int epn;
- const usb_endpoint_descriptor *usb_endpoints;
- cyg_uint8 endpoint_type;
-
- cyg_uint8 endpoint_number;
usbs_end_all_transfers (-EPIPE);
@@ -490,6 +649,18 @@
usbs_at91_endpoint_init ((usbs_rx_endpoint *)usbs_at91_endpoints[epn],
0, false);
}
+}
+
+static void
+usbs_at91_handle_reset (void)
+{
+ int epn;
+ const usb_endpoint_descriptor *usb_endpoints;
+ cyg_uint8 endpoint_type;
+
+ cyg_uint8 endpoint_number;
+
+ usbs_at91_reset_device ();
// Now walk the endpoints configuring them correctly. This only
// works if there is one interface.
@@ -505,11 +676,11 @@
USB_ENDPOINT_DESCRIPTOR_ENDPOINT_IN :
USB_ENDPOINT_DESCRIPTOR_ENDPOINT_OUT));
endpoint_number = usb_endpoints[epn-1].endpoint & ~(USB_ENDPOINT_DESCRIPTOR_ENDPOINT_IN);
- if ( endpoint_number < AT91_USB_ENDPOINTS )
- {
- usbs_at91_endpoint_init((usbs_rx_endpoint *)usbs_at91_endpoints[endpoint_number],
- endpoint_type,
- true);
+
+ if ( endpoint_number < AT91_USB_ENDPOINTS ) {
+ usbs_at91_endpoint_init((usbs_rx_endpoint *)usbs_at91_endpoints[endpoint_number],
+ endpoint_type,
+ true);
}
}
}
@@ -527,6 +698,7 @@
#endif
usbs_at91_set_pullup (true);
+ CLEAR_BITS(AT91_UDP + AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS);
}
static void
@@ -1323,7 +1495,7 @@
HAL_ARM_AT91_GPIO_CFG_DIRECTION(CYGDAT_DEVS_USB_AT91_GPIO_READ_POWER_PIN,
AT91_PIN_IN);
#endif
- usbs_at91_handle_reset ();
+ usbs_at91_reset_device ();
cyg_drv_interrupt_create (CYGNUM_HAL_INTERRUPT_UDP,
6, // priority
@@ -1335,8 +1507,6 @@
cyg_drv_interrupt_attach (usbs_at91_intr_handle);
cyg_drv_interrupt_unmask (CYGNUM_HAL_INTERRUPT_UDP);
- HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_TXVC, 0);
-
usbs_at91_ep0.state = USBS_STATE_POWERED;
usbs_state_notify (&usbs_at91_ep0);
}
Index: devs/usb/at91/current/src/usbs_at91_data.cxx
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/usb/at91/current/src/usbs_at91_data.cxx,v
retrieving revision 1.2
diff -u -r1.2 usbs_at91_data.cxx
--- devs/usb/at91/current/src/usbs_at91_data.cxx 2 Jun 2006 18:46:13 -0000 1.2
+++ devs/usb/at91/current/src/usbs_at91_data.cxx 3 Nov 2008 08:38:39 -0000
@@ -121,14 +121,17 @@
#if defined(CYGVAR_DEVS_USB_AT91_EP1_DEVTAB_ENTRY) || \
defined(CYGVAR_DEVS_USB_AT91_EP2_DEVTAB_ENTRY) || \
- defined(CYGVAR_DEVS_USB_AT91_EP3_DEVTAB_ENTRY)
+ defined(CYGVAR_DEVS_USB_AT91_EP3_DEVTAB_ENTRY) || \
+ defined(CYGVAR_DEVS_USB_AT91_EP4_DEVTAB_ENTRY) || \
+ defined(CYGVAR_DEVS_USB_AT91_EP5_DEVTAB_ENTRY) || \
+ defined(CYGVAR_DEVS_USB_AT91_EP6_DEVTAB_ENTRY) || \
+ defined(CYGVAR_DEVS_USB_AT91_EP7_DEVTAB_ENTRY)
static bool usbs_at91_devtab_dummy_init(struct cyg_devtab_entry* tab){
CYG_UNUSED_PARAM(struct cyg_devtab_entry*, tab);
return true;
}
-
#endif
#ifdef CYGVAR_DEVS_USB_AT91_EP1_DEVTAB_ENTRY
@@ -181,3 +184,71 @@
0,
(void*) &usbs_at91_ep3);
#endif
+
+#ifdef CYGVAR_DEVS_USB_AT91_EP4_DEVTAB_ENTRY
+CHAR_DEVIO_TABLE(usbs_at91_ep4_devtab_functions,
+ &usbs_devtab_cwrite,
+ &usbs_devtab_cread,
+ &cyg_devio_select,
+ &usbs_devtab_get_config,
+ &usbs_devtab_set_config);
+
+CHAR_DEVTAB_ENTRY(usbs_at91_ep4_devtab_entry,
+ CYGDAT_DEVS_USB_AT91_DEVTAB_BASENAME "4",
+ 0,
+ &usbs_at91_ep4_devtab_functions,
+ &usbs_at91_devtab_dummy_init,
+ 0,
+ (void*) &usbs_at91_ep4);
+#endif
+
+#ifdef CYGVAR_DEVS_USB_AT91_EP5_DEVTAB_ENTRY
+CHAR_DEVIO_TABLE(usbs_at91_ep5_devtab_functions,
+ &usbs_devtab_cwrite,
+ &usbs_devtab_cread,
+ &cyg_devio_select,
+ &usbs_devtab_get_config,
+ &usbs_devtab_set_config);
+
+CHAR_DEVTAB_ENTRY(usbs_at91_ep5_devtab_entry,
+ CYGDAT_DEVS_USB_AT91_DEVTAB_BASENAME "5",
+ 0,
+ &usbs_at91_ep5_devtab_functions,
+ &usbs_at91_devtab_dummy_init,
+ 0,
+ (void*) &usbs_at91_ep5);
+#endif
+
+#ifdef CYGVAR_DEVS_USB_AT91_EP6_DEVTAB_ENTRY
+CHAR_DEVIO_TABLE(usbs_at91_ep6_devtab_functions,
+ &usbs_devtab_cwrite,
+ &usbs_devtab_cread,
+ &cyg_devio_select,
+ &usbs_devtab_get_config,
+ &usbs_devtab_set_config);
+
+CHAR_DEVTAB_ENTRY(usbs_at91_ep6_devtab_entry,
+ CYGDAT_DEVS_USB_AT91_DEVTAB_BASENAME "6",
+ 0,
+ &usbs_at91_ep6_devtab_functions,
+ &usbs_at91_devtab_dummy_init,
+ 0,
+ (void*) &usbs_at91_ep6);
+#endif
+
+#ifdef CYGVAR_DEVS_USB_AT91_EP7_DEVTAB_ENTRY
+CHAR_DEVIO_TABLE(usbs_at91_ep7_devtab_functions,
+ &usbs_devtab_cwrite,
+ &usbs_devtab_cread,
+ &cyg_devio_select,
+ &usbs_devtab_get_config,
+ &usbs_devtab_set_config);
+
+CHAR_DEVTAB_ENTRY(usbs_at91_ep7_devtab_entry,
+ CYGDAT_DEVS_USB_AT91_DEVTAB_BASENAME "7",
+ 0,
+ &usbs_at91_ep7_devtab_functions,
+ &usbs_at91_devtab_dummy_init,
+ 0,
+ (void*) &usbs_at91_ep7);
+#endif
Index: hal/arm/at91/at91sam7s/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/ChangeLog,v
retrieving revision 1.20
diff -u -r1.20 ChangeLog
--- hal/arm/at91/at91sam7s/current/ChangeLog 19 Oct 2008 14:51:33 -0000 1.20
+++ hal/arm/at91/at91sam7s/current/ChangeLog 3 Nov 2008 08:38:39 -0000
@@ -1,3 +1,15 @@
+2009-11-03 Gabor Toeroek <tgabor84@gmail.com>
+
+ * cdl/hal_arm_at91sam7s.cdl
+ * include/hal_platform_ints.h
+ * include/plf_io.h
+ * include/var_io.h: Add support for AT91SAM7SE
+
+2009-10-31 Oliver Munz" <munz@speag.ch>
+
+ * cdl/hal_arm_at91sam7s.cdl: Allow external clock input to be up
+ to 50Mhz, but the crystal is limited to 30MHz.
+
2008-10-19 Igor B. Poretsky <poretsky@mlbox.ru>
Andrew Lunn <andrew.lunn@ascom.ch>
Index: hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl,v
retrieving revision 1.12
diff -u -r1.12 hal_arm_at91sam7s.cdl
--- hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl 19 Oct 2008 14:51:33 -0000 1.12
+++ hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl 3 Nov 2008 08:38:39 -0000
@@ -77,7 +77,8 @@
flavor data
default_value {"at91sam7s256"}
legal_values {"at91sam7s32" "at91sam7s321" "at91sam7s64"
- "at91sam7s128" "at91sam7s256"
+ "at91sam7s128" "at91sam7s256" "at91sam7s512"
+ "at91sam7se32" "at91sam7se256" "at91sam7se512"
"at91sam7x128" "at91sam7x256" "at91sam7x512"
"at91sam7xc128" "at91sam7xc256" }
description "
@@ -90,7 +91,8 @@
cdl_option CYGHWR_HAL_ARM_AT91SAM7S {
display "SAM7S device"
- calculated { CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7s256" ||
+ calculated { CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7s512" ||
+ CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7s256" ||
CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7s128" ||
CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7s64" ||
CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7s32" ||
@@ -99,6 +101,15 @@
Is the AT91SAM7 device a member of the AT91SAM7S family?"
}
+ cdl_option CYGHWR_HAL_ARM_AT91SAM7SE {
+ display "SAM7SE device"
+ calculated { CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7se512" ||
+ CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7se256" ||
+ CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7se32" }
+ description "
+ Is the AT91SAM7 device a member of the AT91SAM7SE family?"
+ }
+
cdl_option CYGHWR_HAL_ARM_AT91SAM7X {
display "SAM7X device"
calculated { CYGHWR_HAL_ARM_AT91SAM7 == "at91sam7x512" ||
@@ -119,6 +130,7 @@
cdl_option CYGBLD_HAL_ARM_AT91SAM7_USB {
display "USB device"
active_if {!( "at91sam7s32" == CYGHWR_HAL_ARM_AT91SAM7S) ||
+ CYGHWR_HAL_ARM_AT91SAM7SE ||
CYGHWR_HAL_ARM_AT91SAM7X ||
CYGHWR_HAL_ARM_AT91SAM7XC }
implements CYGINT_DEVS_USB_AT91_HAS_USB
@@ -222,10 +234,22 @@
PLL clock divided by two"
}
+ cdl_option CYGNUM_HAL_ARM_AT91_CLOCK_XIN_FREQ_MAX {
+ display "Input clock frequency maximum"
+ flavor data
+ calculated { CYGNUM_HAL_ARM_AT91_CLOCK_TYPE == "CRYSTAL" ?
+ 20000000 : 50000000 }
+ description "
+
+ The oscilator in the AT91SAM allows a crystal of up to
+ 20MHz. However by feeding in directly a clock signal, it
+ is possible to use upto 50MHz in XIN."
+ }
+
cdl_option CYGNUM_HAL_ARM_AT91_CLOCK_OSC_MAIN {
display "Main oscillator frequency"
flavor data
- legal_values { 3000000 to 20000000}
+ legal_values { 3000000 to CYGNUM_HAL_ARM_AT91_CLOCK_XIN_FREQ_MAX }
default_value { 18432000 }
description "
The frequency of the clock input, be it a crystal or a clock
Index: hal/arm/at91/at91sam7s/current/include/hal_platform_ints.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/include/hal_platform_ints.h,v
retrieving revision 1.2
diff -u -r1.2 hal_platform_ints.h
--- hal/arm/at91/at91sam7s/current/include/hal_platform_ints.h 2 Jun 2006 18:15:29 -0000 1.2
+++ hal/arm/at91/at91sam7s/current/include/hal_platform_ints.h 3 Nov 2008 08:38:39 -0000
@@ -71,6 +71,11 @@
#define CYGNUM_HAL_INTERRUPT_ADC 4
#define CYGNUM_HAL_INTERRUPT_SPI 5
#endif
+#ifdef CYGHWR_HAL_ARM_AT91SAM7SE
+#define CYGNUM_HAL_INTERRUPT_PIOB 3
+#define CYGNUM_HAL_INTERRUPT_PIOC 4
+#define CYGNUM_HAL_INTERRUPT_SPI 5
+#endif
#define CYGNUM_HAL_INTERRUPT_USART0 6
#define CYGNUM_HAL_INTERRUPT_USART1 7
@@ -82,6 +87,9 @@
#define CYGNUM_HAL_INTERRUPT_TC1 13
#define CYGNUM_HAL_INTERRUPT_TC2 14
+#ifdef CYGHWR_HAL_ARM_AT91SAM7SE
+#define CYGNUM_HAL_INTERRUPT_ADC 15
+#endif
#ifdef CYGHWR_HAL_ARM_AT91SAM7X
#define CYGNUM_HAL_INTERRUPT_CAN 15
#define CYGNUM_HAL_INTERRUPT_EMAC 16
Index: hal/arm/at91/at91sam7s/current/include/plf_io.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/at91sam7s/current/include/plf_io.h,v
retrieving revision 1.9
diff -u -r1.9 plf_io.h
--- hal/arm/at91/at91sam7s/current/include/plf_io.h 4 Sep 2008 05:50:26 -0000 1.9
+++ hal/arm/at91/at91sam7s/current/include/plf_io.h 3 Nov 2008 08:38:39 -0000
@@ -76,9 +76,13 @@
// Peripheral Input/Output Controllers
#define AT91_PIOA 0xFFFFF400
-#ifdef CYGHWR_HAL_ARM_AT91SAM7X
+#if defined(CYGHWR_HAL_ARM_AT91SAM7X) || \
+ defined(CYGHWR_HAL_ARM_AT91SAM7SE)
#define AT91_PIOB 0xFFFFF600
#endif
+#if defined(CYGHWR_HAL_ARM_AT91SAM7SE)
+#define AT91_PIOC 0xFFFFF800
+#endif
// USART
@@ -175,7 +179,9 @@
#endif
-#ifdef CYGHWR_HAL_ARM_AT91SAM7_at91sam7x512
+#if defined(CYGHWR_HAL_ARM_AT91SAM7_at91sam7x512) || \
+ defined(CYGHWR_HAL_ARM_AT91SAM7_at91sam7s512) || \
+ defined(CYGHWR_HAL_ARM_AT91SAM7_at91sam7se512)
#define AT91_MC_FMR0 0x60
#define AT91_MC_FMR1 0x70
#define AT91_MC_FMR AT91_MC_FMR0
@@ -197,6 +203,5 @@
#endif //__ASSEMBLER__
-
#endif //CYGONCE_HAL_PLF_IO_H
Index: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s512_rom.h
===================================================================
RCS file: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s512_rom.h
diff -N hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s512_rom.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s512_rom.h 3 Nov 2008 08:38:39 -0000
@@ -0,0 +1,25 @@
+// eCos memory layout - Thu Oct 09 03:46 2008
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x00200000)
+#define CYGMEM_REGION_ram_SIZE (0x10000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0x00100000)
+#define CYGMEM_REGION_rom_SIZE (0x80000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_bootmon) [];
+#endif
+#define CYGMEM_SECTION_reserved_bootmon (CYG_LABEL_NAME (__reserved_bootmon))
+#define CYGMEM_SECTION_reserved_bootmon_SIZE (0x01000)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (0x00210000 - (size_t) CYG_LABEL_NAME (__heap1))
Index: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s512_rom.ldi
===================================================================
RCS file: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s512_rom.ldi
diff -N hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s512_rom.ldi
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7s512_rom.ldi 3 Nov 2008 08:38:39 -0000
@@ -0,0 +1,30 @@
+// eCos memory layout - Thu Oct 09 03:46 2008
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+#include <pkgconf/hal_arm_at91sam7.h>
+
+MEMORY
+{
+ ram : ORIGIN = 0x00200000, LENGTH = 0x10000
+ rom : ORIGIN = 0x00100000, LENGTH = 0x80000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ CYG_LABEL_DEFN(__reserved_bootmon) = 0x00000000; . = CYG_LABEL_DEFN(__reserved_bootmon) + 0x01000;
+ SECTION_rom_vectors (rom, CYGNUM_HAL_ARM_AT91_IMAGE_ADDRESS, LMA_EQ_VMA)
+ SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA)
+ SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixed_vectors (ram, 0x00200040, LMA_EQ_VMA)
+ SECTION_data (ram, ALIGN (0x4), FOLLOWING (.gcc_except_table))
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
Index: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se256_rom.h
===================================================================
RCS file: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se256_rom.h
diff -N hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se256_rom.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se256_rom.h 3 Nov 2008 08:38:39 -0000
@@ -0,0 +1,25 @@
+// eCos memory layout - Thu Oct 09 03:51 2008
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x00200000)
+#define CYGMEM_REGION_ram_SIZE (0x8000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0x00100000)
+#define CYGMEM_REGION_rom_SIZE (0x40000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_bootmon) [];
+#endif
+#define CYGMEM_SECTION_reserved_bootmon (CYG_LABEL_NAME (__reserved_bootmon))
+#define CYGMEM_SECTION_reserved_bootmon_SIZE (0x01000)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (0x00208000 - (size_t) CYG_LABEL_NAME (__heap1))
Index: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se256_rom.ldi
===================================================================
RCS file: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se256_rom.ldi
diff -N hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se256_rom.ldi
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se256_rom.ldi 3 Nov 2008 08:38:39 -0000
@@ -0,0 +1,30 @@
+// eCos memory layout - Thu Oct 09 03:51 2008
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+#include <pkgconf/hal_arm_at91sam7.h>
+
+MEMORY
+{
+ ram : ORIGIN = 0x00200000, LENGTH = 0x08000
+ rom : ORIGIN = 0x00100000, LENGTH = 0x40000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ CYG_LABEL_DEFN(__reserved_bootmon) = 0x00000000; . = CYG_LABEL_DEFN(__reserved_bootmon) + 0x01000;
+ SECTION_rom_vectors (rom, CYGNUM_HAL_ARM_AT91_IMAGE_ADDRESS, LMA_EQ_VMA)
+ SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA)
+ SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixed_vectors (ram, 0x00200040, LMA_EQ_VMA)
+ SECTION_data (ram, ALIGN (0x4), FOLLOWING (.gcc_except_table))
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
Index: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se32_rom.h
===================================================================
RCS file: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se32_rom.h
diff -N hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se32_rom.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se32_rom.h 3 Nov 2008 08:38:39 -0000
@@ -0,0 +1,25 @@
+// eCos memory layout - Wed Apr 11 13:49:55 2001
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x00200000)
+#define CYGMEM_REGION_ram_SIZE (0x02000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0x00100000)
+#define CYGMEM_REGION_rom_SIZE (0x08000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_bootmon) [];
+#endif
+#define CYGMEM_SECTION_reserved_bootmon (CYG_LABEL_NAME (__reserved_bootmon))
+#define CYGMEM_SECTION_reserved_bootmon_SIZE (0x01000)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (0x00202000 - (size_t) CYG_LABEL_NAME (__heap1))
Index: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se32_rom.ldi
===================================================================
RCS file: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se32_rom.ldi
diff -N hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se32_rom.ldi
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se32_rom.ldi 3 Nov 2008 08:38:39 -0000
@@ -0,0 +1,30 @@
+// eCos memory layout - Wed Apr 11 13:49:55 2001
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+#include <pkgconf/hal_arm_at91sam7.h>
+
+MEMORY
+{
+ ram : ORIGIN = 0x00200000, LENGTH = 0x02000
+ rom : ORIGIN = 0x00100000, LENGTH = 0x08000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ CYG_LABEL_DEFN(__reserved_bootmon) = 0x00000000; . = CYG_LABEL_DEFN(__reserved_bootmon) + 0x01000;
+ SECTION_rom_vectors (rom, CYGNUM_HAL_ARM_AT91_IMAGE_ADDRESS, LMA_EQ_VMA)
+ SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA)
+ SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixed_vectors (ram, 0x00200040, LMA_EQ_VMA)
+ SECTION_data (ram, ALIGN (0x4), FOLLOWING (.gcc_except_table))
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
Index: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se512_rom.h
===================================================================
RCS file: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se512_rom.h
diff -N hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se512_rom.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se512_rom.h 3 Nov 2008 08:38:39 -0000
@@ -0,0 +1,25 @@
+// eCos memory layout - Thu Oct 09 03:51 2008
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x00200000)
+#define CYGMEM_REGION_ram_SIZE (0x8000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0x00100000)
+#define CYGMEM_REGION_rom_SIZE (0x80000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__reserved_bootmon) [];
+#endif
+#define CYGMEM_SECTION_reserved_bootmon (CYG_LABEL_NAME (__reserved_bootmon))
+#define CYGMEM_SECTION_reserved_bootmon_SIZE (0x01000)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (0x00208000 - (size_t) CYG_LABEL_NAME (__heap1))
Index: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se512_rom.ldi
===================================================================
RCS file: hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se512_rom.ldi
diff -N hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se512_rom.ldi
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ hal/arm/at91/at91sam7s/current/include/pkgconf/mlt_arm_at91sam7se512_rom.ldi 3 Nov 2008 08:38:39 -0000
@@ -0,0 +1,30 @@
+// eCos memory layout - Thu Oct 09 03:51 2008
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+#include <pkgconf/hal_arm_at91sam7.h>
+
+MEMORY
+{
+ ram : ORIGIN = 0x00200000, LENGTH = 0x08000
+ rom : ORIGIN = 0x00100000, LENGTH = 0x80000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ CYG_LABEL_DEFN(__reserved_bootmon) = 0x00000000; . = CYG_LABEL_DEFN(__reserved_bootmon) + 0x01000;
+ SECTION_rom_vectors (rom, CYGNUM_HAL_ARM_AT91_IMAGE_ADDRESS, LMA_EQ_VMA)
+ SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA)
+ SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixed_vectors (ram, 0x00200040, LMA_EQ_VMA)
+ SECTION_data (ram, ALIGN (0x4), FOLLOWING (.gcc_except_table))
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
Index: hal/arm/at91/var/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/ChangeLog,v
retrieving revision 1.43
diff -u -r1.43 ChangeLog
--- hal/arm/at91/var/current/ChangeLog 19 Oct 2008 14:51:08 -0000 1.43
+++ hal/arm/at91/var/current/ChangeLog 3 Nov 2008 08:38:40 -0000
@@ -1,8 +1,12 @@
+2008-11-03 Gabor Toeroek <tgabor84@gmail.com>
+
+ * include/var_io.h: Added defines for AT91SAM7SE.
+
2008-10-19 Igor B. Poretsky <poretsky@mlbox.ru>
* include/var_io.h Fixed various typos.
-2008-09-02 John Eigelaar <jeigelaar@mweb.co.za>
+2008-09-02 John Eigelaar: <jeigelaar@mweb.co.za>
* include/var_io.h: Added support for a second flash controller.
Fixed some cut and paste gremlins in the SSC definitions.
Index: hal/arm/at91/var/current/include/var_io.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/at91/var/current/include/var_io.h,v
retrieving revision 1.22
diff -u -r1.22 var_io.h
--- hal/arm/at91/var/current/include/var_io.h 19 Oct 2008 14:51:08 -0000 1.22
+++ hal/arm/at91/var/current/include/var_io.h 3 Nov 2008 08:38:42 -0000
@@ -244,6 +244,42 @@
#define AT91_GPIO_PB31 AT91_PIN(1,0,31)
#endif //AT91_PIOB
+#ifdef AT91_PIOC
+// GPIO pins on PIOC.
+#define AT91_GPIO_PC0 AT91_PIN(2,0, 0)
+#define AT91_GPIO_PC1 AT91_PIN(2,0, 1)
+#define AT91_GPIO_PC2 AT91_PIN(2,0, 2)
+#define AT91_GPIO_PC3 AT91_PIN(2,0, 3)
+#define AT91_GPIO_PC4 AT91_PIN(2,0, 4)
+#define AT91_GPIO_PC5 AT91_PIN(2,0, 5)
+#define AT91_GPIO_PC6 AT91_PIN(2,0, 6)
+#define AT91_GPIO_PC7 AT91_PIN(2,0, 7)
+#define AT91_GPIO_PC8 AT91_PIN(2,0, 8)
+#define AT91_GPIO_PC9 AT91_PIN(2,0, 9)
+#define AT91_GPIO_PC10 AT91_PIN(2,0,10)
+#define AT91_GPIO_PC11 AT91_PIN(2,0,11)
+#define AT91_GPIO_PC12 AT91_PIN(2,0,12)
+#define AT91_GPIO_PC13 AT91_PIN(2,0,13)
+#define AT91_GPIO_PC14 AT91_PIN(2,0,14)
+#define AT91_GPIO_PC15 AT91_PIN(2,0,15)
+#define AT91_GPIO_PC16 AT91_PIN(2,0,16)
+#define AT91_GPIO_PC17 AT91_PIN(2,0,17)
+#define AT91_GPIO_PC18 AT91_PIN(2,0,18)
+#define AT91_GPIO_PC19 AT91_PIN(2,0,19)
+#define AT91_GPIO_PC20 AT91_PIN(2,0,20)
+#define AT91_GPIO_PC21 AT91_PIN(2,0,21)
+#define AT91_GPIO_PC22 AT91_PIN(2,0,22)
+#define AT91_GPIO_PC23 AT91_PIN(2,0,23)
+#define AT91_GPIO_PC24 AT91_PIN(2,0,24)
+#define AT91_GPIO_PC25 AT91_PIN(2,0,25)
+#define AT91_GPIO_PC26 AT91_PIN(2,0,26)
+#define AT91_GPIO_PC27 AT91_PIN(2,0,27)
+#define AT91_GPIO_PC28 AT91_PIN(2,0,28)
+#define AT91_GPIO_PC29 AT91_PIN(2,0,29)
+#define AT91_GPIO_PC30 AT91_PIN(2,0,30)
+#define AT91_GPIO_PC31 AT91_PIN(2,0,31)
+#endif //AT91_PIOC
+
#if defined(CYGHWR_HAL_ARM_AT91_M55800A)
#define AT91_TC_TCLK3 AT91_PIN(0,0, 0) // Timer 3 Clock signal
@@ -448,7 +484,7 @@
#define AT91_PIO_PSR_RI1 0x20000000 // USART 2 Ring Indicator
#define AT91_PIO_PSR_IRQ1 0x40000000 // Interrupt Request 1
#define AT91_PIO_PSR_NPCS1 0x80000000 // SPI Chip Select 1
-#endif // !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s64)
+#endif // !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
// PIO Peripheral B
#define AT91_PIO_PSR_TIOA0 0x00000001 // Timer/Counter 0 IO Line A
@@ -484,7 +520,7 @@
#define AT91_PIO_PSR_TCLK2 0x20000000 // External Clock Input 2
#define AT91_PIO_PSR_NPCS2X 0x40000000 // SPI Chip Select 2 (again)
#define AT91_PIO_PSR_PCK2X 0x80000000 // Programmable Clock Output 2(again)
-#endif // !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s64)
+#endif // !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
#endif // CYGHWR_HAL_ARM_AT91SAM7S
#ifdef CYGHWR_HAL_ARM_AT91SAM7X
@@ -707,12 +743,405 @@
#define AT91_PIO_PSR_PWM1X (1<<28) // Pulse Width Modulation #1
#define AT91_PIO_PSR_PWM2X (1<<29) // Pulse Width Modulation #2
#define AT91_PIO_PSR_PWM3X (1<<30) // Pulse Width Modulation #3
-#endif
+#endif // CYGHWR_HAL_ARM_AT91SAM7X
#ifdef CYGHWR_HAL_ARM_AT91SAM7XC
#error Sorry, still missing. Happy typing
#endif
+#ifdef CYGHWR_HAL_ARM_AT91SAM7SE
+//PIO Controller A Peripheral A
+#define AT91_PWM_PWM0 AT91_PIN(0,0, 0) // Pulse Width Modulation 0
+#define AT91_PWM_PWM1 AT91_PIN(0,0, 1) // Pulse Width Modulation 1
+#define AT91_PWM_PWM2 AT91_PIN(0,0, 2) // Pulse Width Modulation 2
+#define AT91_TWI_TWD AT91_PIN(0,0, 3) // Two Wire Data
+#define AT91_TWI_TWCK AT91_PIN(0,0, 4) // Two Wire Clock
+#define AT91_USART_RXD0 AT91_PIN(0,0, 5) // USART 0 Receive Data
+#define AT91_USART_TXD0 AT91_PIN(0,0, 6) // USART 0 Transmit Data
+#define AT91_USART_RTS0 AT91_PIN(0,0, 7) // USART 0 Ready To Send
+#define AT91_USART_CTS0 AT91_PIN(0,0, 8) // USART 0 Clear To Send
+#define AT91_DBG_DRXD AT91_PIN(0,0, 9) // Debug UART Receive
+#define AT91_DBG_DTXD AT91_PIN(0,0,10) // Debug UART Transmit
+#define AT91_SPI_NPCS0 AT91_PIN(0,0,11) // SPI Chip Select 0
+#define AT91_SPI_MISO AT91_PIN(0,0,12) // SPI Input
+#define AT91_SPI_MOSI AT91_PIN(0,0,13) // SPI Output
+#define AT91_SPI_SPCK AT91_PIN(0,0,14) // SPI clock
+#define AT91_S2C_TF AT91_PIN(0,0,15) // S2C Transmit Frame Sync
+#define AT91_S2C_TK AT91_PIN(0,0,16) // S2C Transmit Clock
+#define AT91_S2C_TD AT91_PIN(0,0,17) // S2C Transmit Data
+#define AT91_S2C_RD AT91_PIN(0,0,18) // S2C Receive Data
+#define AT91_S2C_RK AT91_PIN(0,0,19) // S2C Receive Clock
+#define AT91_S2C_RF AT91_PIN(0,0,20) // S2C Receive Frame Sync
+#define AT91_USART_RXD1 AT91_PIN(0,0,21) // USART 1 Receive Data
+#define AT91_USART_TXD1 AT91_PIN(0,0,22) // USART 1 Transmit Data
+#define AT91_USART_SCK1 AT91_PIN(0,0,23) // USART 1 Serial Clock
+#define AT91_USART_RTS1 AT91_PIN(0,0,24) // USART 1 Ready To Send
+#define AT91_USART_CTS1 AT91_PIN(0,0,25) // USART 1 Clear To Send
+#define AT91_USART_DVD1 AT91_PIN(0,0,26) // USART 1 Data Carrier Detect
+#define AT91_USART_DTR1 AT91_PIN(0,0,27) // USART 1 Data Terminal Ready
+#define AT91_USART_DSR1 AT91_PIN(0,0,28) // USART 1 Data Set Ready
+#define AT91_USART_RI1 AT91_PIN(0,0,29) // USART 2 Ring Indicator
+#define AT91_INT_IRQ1 AT91_PIN(0,0,30) // Interrupt Request 1
+#define AT91_SPI_NPCS1 AT91_PIN(0,0,31) // SPI Chip Select 1
+
+//PIO Controller A Peripheral B
+#define AT91_EBI_A0_NBS0 AT91_PIN(0,1, 0) // EBI: Addr 0 / SDRAM Byte Mask 0
+#define AT91_EBI_A1_NBS2 AT91_PIN(0,1, 1) // EBI: Addr 1 / SDRAM Byte Mask 2
+#define AT91_EBI_A2 AT91_PIN(0,1, 2) // EBI: Addr 2
+#define AT91_EBI_A3 AT91_PIN(0,1, 3) // EBI: Addr 3
+#define AT91_EBI_A4 AT91_PIN(0,1, 4) // EBI: Addr 4
+#define AT91_EBI_A5 AT91_PIN(0,1, 5) // EBI: Addr 5
+#define AT91_EBI_A6 AT91_PIN(0,1, 6) // EBI: Addr 6
+#define AT91_EBI_A7 AT91_PIN(0,1, 7) // EBI: Addr 7
+#define AT91_EBI_A8 AT91_PIN(0,1, 8) // EBI: Addr 8
+#define AT91_EBI_A9 AT91_PIN(0,1, 9) // EBI: Addr 9
+#define AT91_EBI_A10 AT91_PIN(0,1,10) // EBI: Addr 10
+#define AT91_EBI_A11 AT91_PIN(0,1,11) // EBI: Addr 11
+#define AT91_EBI_A12 AT91_PIN(0,1,12) // EBI: Addr 12
+#define AT91_EBI_A13 AT91_PIN(0,1,13) // EBI: Addr 13
+#define AT91_EBI_A14 AT91_PIN(0,1,14) // EBI: Addr 14
+#define AT91_EBI_A15 AT91_PIN(0,1,15) // EBI: Addr 15
+#define AT91_EBI_A16_BA0 AT91_PIN(0,1,16) // EBI: Addr 16 / SDRAM Bank Sel 0
+#define AT91_EBI_A17_BA1 AT91_PIN(0,1,17) // EBI: Addr 17 / SDRAM Bank Sel 1
+#define AT91_EBI_NBS3_CFIOW AT91_PIN(0,1,18) // EBI: SDRAM Byte Mask 3 /
+ // CompactFlash I/O Write Signal
+#define AT91_EBI_NCS4_CFCS0 AT91_PIN(0,1,19) // EBI: Chip Select 4 /
+ // CompactFlash Chip Select 0
+#define AT91_EBI_NCS2_CFCS1 AT91_PIN(0,1,20) // EBI: Chip Select 2 /
+ // CompactFlash Chip Select 1
+#define AT91_EBI_NCS6_CFCE2 AT91_PIN(0,1,21) // EBI: Chip Select 6 /
+ // CompactFlash Chip Enable 2
+#define AT91_EBI_NCS5_CFCE1 AT91_PIN(0,1,22) // EBI: Chip Select 5 /
+ // CompactFlash Chip Enable 1
+#define AT91_EBI_NWR1_NBS1_CFIOR \
+ AT91_PIN(0,1,23) // EBI: SMC Write 1 /
+ // SDRAM Byte Mask 1 /
+ // CompactFlash I/O Read Signal
+#define AT91_EBI_SDA10 AT91_PIN(0,1,24) // EBI: SDRAM Address 10
+#define AT91_EBI_SDCKE AT91_PIN(0,1,25) // EBI: SDRAM Clock Enable
+#define AT91_EBI_NCS1_SDCS AT91_PIN(0,1,26) // EBI: Chip Select 1 /
+ // SDRAM Controller Chip Select
+#define AT91_EBI_SDWE AT91_PIN(0,1,27) // EBI: SDRAM Write Enable
+#define AT91_EBI_CAS AT91_PIN(0,1,28) // EBI: SDRAM Column Signal
+#define AT91_EBI_RAS AT91_PIN(0,1,29) // EBI: SDRAM Row Signal
+#define AT91_EBI_D30 AT91_PIN(0,1,30) // EBI: Data 30
+#define AT91_EBI_D31 AT91_PIN(0,1,31) // EBI: Data 31
+
+//PIO Controller A Peripheral A
+#define AT91_PIO_PSR_PWM0 (1<< 0) // Pulse Width Modulation 0
+#define AT91_PIO_PSR_PWM1 (1<< 1) // Pulse Width Modulation 1
+#define AT91_PIO_PSR_PWM2 (1<< 2) // Pulse Width Modulation 2
+#define AT91_PIO_PSR_TWD (1<< 3) // Two Wire Data
+#define AT91_PIO_PSR_TWCK (1<< 4) // Two Wire Clock
+#define AT91_PIO_PSR_RXD0 (1<< 5) // USART 0 Receive Data
+#define AT91_PIO_PSR_TXD0 (1<< 6) // USART 0 Transmit Data
+#define AT91_PIO_PSR_RTS0 (1<< 7) // USART 0 Ready To Send
+#define AT91_PIO_PSR_CTS0 (1<< 8) // USART 0 Clear To Send
+#define AT91_PIO_PSR_DRXD (1<< 9) // Debug UART Receive
+#define AT91_PIO_PSR_DTXD (1<<10) // Debug UART Transmit
+#define AT91_PIO_PSR_NPCS0 (1<<11) // SPI Chip Select 0
+#define AT91_PIO_PSR_MISO (1<<12) // SPI Input
+#define AT91_PIO_PSR_MOSI (1<<13) // SPI Output
+#define AT91_PIO_PSR_SPCK (1<<14) // SPI clock
+#define AT91_PIO_PSR_TF (1<<15) // S2C Transmit Frame Sync
+#define AT91_PIO_PSR_TK (1<<16) // S2C Transmit Clock
+#define AT91_PIO_PSR_TD (1<<17) // S2C Transmit Data
+#define AT91_PIO_PSR_RD (1<<18) // S2C Receive Data
+#define AT91_PIO_PSR_RK (1<<19) // S2C Receive Clock
+#define AT91_PIO_PSR_RF (1<<20) // S2C Receive Frame Sync
+#define AT91_PIO_PSR_RXD1 (1<<21) // USART 1 Receive Data
+#define AT91_PIO_PSR_TXD1 (1<<22) // USART 1 Transmit Data
+#define AT91_PIO_PSR_SCK1 (1<<23) // USART 1 Serial Clock
+#define AT91_PIO_PSR_RTS1 (1<<24) // USART 1 Ready To Send
+#define AT91_PIO_PSR_CTS1 (1<<25) // USART 1 Clear To Send
+#define AT91_PIO_PSR_DVD1 (1<<26) // USART 1 Data Carrier Detect
+#define AT91_PIO_PSR_DTR1 (1<<27) // USART 1 Data Terminal Ready
+#define AT91_PIO_PSR_DSR1 (1<<28) // USART 1 Data Set Ready
+#define AT91_PIO_PSR_RI1 (1<<29) // USART 2 Ring Indicator
+#define AT91_PIO_PSR_IRQ1 (1<<30) // Interrupt Request 1
+#define AT91_PIO_PSR_NPCS1 (1<<31) // SPI Chip Select 1
+
+//PIO Controller A Peripheral B
+#define AT91_PIO_PSR_A0_NBS0 (1<< 0) // EBI: Address 0 / SDRAM Byte Mask 0
+#define AT91_PIO_PSR_A1_NBS2 (1<< 1) // EBI: Address 1 / SDRAM Byte Mask 2
+#define AT91_PIO_PSR_A2 (1<< 2) // EBI: Address 2
+#define AT91_PIO_PSR_A3 (1<< 3) // EBI: Address 3
+#define AT91_PIO_PSR_A4 (1<< 4) // EBI: Address 4
+#define AT91_PIO_PSR_A5 (1<< 5) // EBI: Address 5
+#define AT91_PIO_PSR_A6 (1<< 6) // EBI: Address 6
+#define AT91_PIO_PSR_A7 (1<< 7) // EBI: Address 7
+#define AT91_PIO_PSR_A8 (1<< 8) // EBI: Address 8
+#define AT91_PIO_PSR_A9 (1<< 9) // EBI: Address 9
+#define AT91_PIO_PSR_A10 (1<<10) // EBI: Address 10
+#define AT91_PIO_PSR_A11 (1<<11) // EBI: Address 11
+#define AT91_PIO_PSR_A12 (1<<12) // EBI: Address 12
+#define AT91_PIO_PSR_A13 (1<<13) // EBI: Address 13
+#define AT91_PIO_PSR_A14 (1<<14) // EBI: Address 14
+#define AT91_PIO_PSR_A15 (1<<15) // EBI: Address 15
+#define AT91_PIO_PSR_A16_BA0 (1<<16) // EBI: Address 16 / SDRAM Bank Sel 0
+#define AT91_PIO_PSR_A17_BA1 (1<<17) // EBI: Address 17 / SDRAM Bank Sel 1
+#define AT91_PIO_PSR_NBS3_CFIOW (1<<18) // EBI: SDRAM Byte Mask 3 /
+ // CompactFlash I/O Write Signal
+#define AT91_PIO_PSR_NCS4_CFCS0 (1<<19) // EBI: Chip Select 4 /
+ // CompactFlash Chip Select 0
+#define AT91_PIO_PSR_NCS2_CFCS1 (1<<20) // EBI: Chip Select 2 /
+ // CompactFlash Chip Select 1
+#define AT91_PIO_PSR_NCS6_CFCE2 (1<<21) // EBI: Chip Select 6 /
+ // CompactFlash Chip Enable 2
+#define AT91_PIO_PSR_NCS5_CFCE1 (1<<22) // EBI: Chip Select 5 /
+ // CompactFlash Chip Enable 1
+#define AT91_PIO_PSR_NWR1_NBS1_CFIOR \
+ (1<<23) // EBI: Write 1 / SDRAM Byte Mask 1 /
+ // CompactFlash I/O Read Signal
+#define AT91_PIO_PSR_SDA10 (1<<24) // EBI: SDRAM Address 10
+#define AT91_PIO_PSR_SDCKE (1<<25) // EBI: SDRAM Clock Enable
+#define AT91_PIO_PSR_NCS1_SDCS (1<<26) // EBI: Chip Select 1 /
+ // SDRAM Controller Chip Select
+#define AT91_PIO_PSR_SDWE (1<<27) // EBI: SDRAM Write Enable
+#define AT91_PIO_PSR_CAS (1<<28) // EBI: SDRAM Column Signal
+#define AT91_PIO_PSR_RAS (1<<29) // EBI: SDRAM Row Signal
+#define AT91_PIO_PSR_D30 (1<<30) // EBI: Data 30
+#define AT91_PIO_PSR_D31 (1<<31) // EBI: Data 31
+
+//PIO Controller B Peripheral A
+#define AT91_TC_TIOA0 AT91_PIN(1,0, 0) // Timer/Counter 0 IO Line A
+#define AT91_TC_TIOB0 AT91_PIN(1,0, 1) // Timer/Counter 0 IO Line B
+#define AT91_USART_SCK0 AT91_PIN(1,0, 2) // USART 0 Serial Clock
+#define AT91_SPI_NPCS3 AT91_PIN(1,0, 3) // SPI Chip Select 3
+#define AT91_TC_TCLK0 AT91_PIN(1,0, 4) // Timer/Counter 0 Clock Input
+#define AT91_SPI_NPCS3X AT91_PIN(1,0, 5) // SPI Chip Select 3 (again)
+#define AT91_PCK_PCK0 AT91_PIN(1,0, 6) // Programmable Clock Output 0
+#define AT91_PWM_PWM3 AT91_PIN(1,0, 7) // Pulse Width Modulation #3
+#define AT91_ADC_ADTRG AT91_PIN(1,0, 8) // ADC Trigger
+#define AT91_SPI_NPCS1X AT91_PIN(1,0, 9) // SPI Chip Select 1
+#define AT91_SPI_NPCS2 AT91_PIN(1,0,10) // SPI Chip Select 2
+#define AT91_PWM_PWM0X AT91_PIN(1,0,11) // Pulse Width Modulation #0
+#define AT91_PIO_PWM_PWM1X AT91_PIN(1,0,12) // Pulse Width Modulation #1
+#define AT91_PIO_PWM_PWM2X AT91_PIN(1,0,13) // Pulse Width Modulation #2
+#define AT91_PIO_PWM_PWM4X AT91_PIN(1,0,14) // Pulse Width Modulation #4
+#define AT91_TC_TIOA1 AT91_PIN(1,0,15) // Timer/Counter 1 IO Line A
+#define AT91_TC_TIOB1 AT91_PIN(1,0,16) // Timer/Counter 1 IO Line B
+#define AT91_PCK_PCK1 AT91_PIN(1,0,17) // Programmable Clock Output 1
+#define AT91_PCK_PCK2 AT91_PIN(1,0,18) // Programmable Clock Output 2
+#define AT91_INT_FIQ AT91_PIN(1,0,19) // Fast Interrupt Request
+#define AT91_INT_IRQ0 AT91_PIN(1,0,20) // Interrupt Request 0
+#define AT91_PCK_PCK1X AT91_PIN(1,0,21) // Programmable Clock Output 1
+#define AT91_SPI_NPCS3XX AT91_PIN(1,0,22) // SPI Chip Select 3 (yet again)
+#define AT91_PWM_PWM0XX AT91_PIN(1,0,23) // Pulse Width Modulation #0
+#define AT91_PWM_PWM1XX AT91_PIN(1,0,24) // Pulse Width Modulation #1
+#define AT91_PWM_PWM2XX AT91_PIN(1,0,25) // Pulse Width Modulation 2
+#define AT91_TC_TIOA2 AT91_PIN(1,0,26) // Timer/Counter 2 IO Line A
+#define AT91_TC_TIOB2 AT91_PIN(1,0,27) // Timer/Counter 2 IO Line B
+#define AT91_TC_TCLK1 AT91_PIN(1,0,28) // External Clock Input 1
+#define AT91_TC_TCLK2 AT91_PIN(1,0,29) // External Clock Input 2
+#define AT91_SPI_NPCS2X AT91_PIN(1,0,30) // SPI Chip Select 2 (again)
+#define AT91_PCK_PCK2X AT91_PIN(1,0,31) // Programmable Clock Output 2
+
+//PIO Controller B Peripheral B
+#define AT91_EBI_A0_NBS0X AT91_PIN(1,1, 0) // EBI: Addr 0 / SDRAM Byte Mask 0
+#define AT91_EBI_A1_NBS2X AT91_PIN(1,1, 1) // EBI: Addr 1 / SDRAM Byte Mask 2
+#define AT91_EBI_A2X AT91_PIN(1,1, 2) // EBI: Addr 2
+#define AT91_EBI_A3X AT91_PIN(1,1, 3) // EBI: Addr 3
+#define AT91_EBI_A4X AT91_PIN(1,1, 4) // EBI: Addr 4
+#define AT91_EBI_A5X AT91_PIN(1,1, 5) // EBI: Addr 5
+#define AT91_EBI_A6X AT91_PIN(1,1, 6) // EBI: Addr 6
+#define AT91_EBI_A7X AT91_PIN(1,1, 7) // EBI: Addr 7
+#define AT91_EBI_A8X AT91_PIN(1,1, 8) // EBI: Addr 8
+#define AT91_EBI_A9X AT91_PIN(1,1, 9) // EBI: Addr 9
+#define AT91_EBI_A10X AT91_PIN(1,1,10) // EBI: Addr 10
+#define AT91_EBI_A11X AT91_PIN(1,1,11) // EBI: Addr 11
+#define AT91_EBI_A12X AT91_PIN(1,1,12) // EBI: Addr 12
+#define AT91_EBI_A13X AT91_PIN(1,1,13) // EBI: Addr 13
+#define AT91_EBI_A14X AT91_PIN(1,1,14) // EBI: Addr 14
+#define AT91_EBI_A15X AT91_PIN(1,1,15) // EBI: Addr 15
+#define AT91_EBI_A16_BA0X AT91_PIN(1,1,16) // EBI: Addr 16 /
+ // SDRAM Bank Select 0
+#define AT91_EBI_A17_BA1X AT91_PIN(1,1,17) // EBI: Addr 17 /
+ // SDRAM Bank Select 1
+#define AT91_EBI_D16 AT91_PIN(1,1,18) // EBI: Data 16
+#define AT91_EBI_D17 AT91_PIN(1,1,19) // EBI: Data 17
+#define AT91_EBI_D18 AT91_PIN(1,1,20) // EBI: Data 18
+#define AT91_EBI_D19 AT91_PIN(1,1,21) // EBI: Data 19
+#define AT91_EBI_D20 AT91_PIN(1,1,22) // EBI: Data 20
+#define AT91_EBI_D21 AT91_PIN(1,1,23) // EBI: Data 21
+#define AT91_EBI_D22 AT91_PIN(1,1,24) // EBI: Data 22
+#define AT91_EBI_D23 AT91_PIN(1,1,25) // EBI: Data 23
+#define AT91_EBI_D24 AT91_PIN(1,1,26) // EBI: Data 24
+#define AT91_EBI_D25 AT91_PIN(1,1,27) // EBI: Data 25
+#define AT91_EBI_D26 AT91_PIN(1,1,28) // EBI: Data 26
+#define AT91_EBI_D27 AT91_PIN(1,1,29) // EBI: Data 27
+#define AT91_EBI_D28 AT91_PIN(1,1,30) // EBI: Data 28
+#define AT91_EBI_D29 AT91_PIN(1,1,31) // EBI: Data 29
+
+//PIO Controller B Peripheral A
+#define AT91_PIO_PSR_TIOA0 (1<< 0) // Timer/Counter 0 IO Line A
+#define AT91_PIO_PSR_TIOB0 (1<< 1) // Timer/Counter 0 IO Line B
+#define AT91_PIO_PSR_SCK0 (1<< 2) // USART 0 Serial Clock
+#define AT91_PIO_PSR_NPCS3 (1<< 3) // SPI Chip Select 3
+#define AT91_PIO_PSR_TCLK0 (1<< 4) // Timer/Counter 0 Clock Input
+#define AT91_PIO_PSR_NPCS3X (1<< 5) // SPI Chip Select 3 (again)
+#define AT91_PIO_PSR_PCK0 (1<< 6) // Programmable Clock Output 0
+#define AT91_PIO_PSR_PWM3 (1<< 7) // Pulse Width Modulation #3
+#define AT91_PIO_PSR_ADTRG (1<< 8) // ADC Trigger
+#define AT91_PIO_PSR_NPCS1X (1<< 9) // SPI Chip Select 1
+#define AT91_PIO_PSR_NPCS2 (1<<10) // SPI Chip Select 2
+#define AT91_PIO_PSR_PWM0X (1<<11) // Pulse Width Modulation #0
+#define AT91_PIO_PSR_PWM1X (1<<12) // Pulse Width Modulation #1
+#define AT91_PIO_PSR_PWM2X (1<<13) // Pulse Width Modulation #2
+#define AT91_PIO_PSR_PWM4X (1<<14) // Pulse Width Modulation #4
+#define AT91_PIO_PSR_TIOA1 (1<<15) // Timer/Counter 1 IO Line A
+#define AT91_PIO_PSR_TIOB1 (1<<16) // Timer/Counter 1 IO Line B
+#define AT91_PIO_PSR_PCK1 (1<<17) // Programmable Clock Output 1
+#define AT91_PIO_PSR_PCK2 (1<<18) // Programmable Clock Output 2
+#define AT91_PIO_PSR_FIQ (1<<19) // Fast Interrupt Request
+#define AT91_PIO_PSR_IRQ0 (1<<20) // Interrupt Request 0
+#define AT91_PIO_PSR_PCK1X (1<<21) // Programmable Clock Output 1
+#define AT91_PIO_PSR_NPCS3XX (1<<22) // SPI Chip Select 3 (yet again)
+#define AT91_PIO_PSR_PWM0XX (1<<23) // Pulse Width Modulation #0
+#define AT91_PIO_PSR_PWM1XX (1<<24) // Pulse Width Modulation #1
+#define AT91_PIO_PSR_PWM2XX (1<<25) // Pulse Width Modulation 2
+#define AT91_PIO_PSR_TIOA2 (1<<26) // Timer/Counter 2 IO Line A
+#define AT91_PIO_PSR_TIOB2 (1<<27) // Timer/Counter 2 IO Line B
+#define AT91_PIO_PSR_TCLK1 (1<<28) // External Clock Input 1
+#define AT91_PIO_PSR_TCLK2 (1<<29) // External Clock Input 2
+#define AT91_PIO_PSR_NPCS2X (1<<30) // SPI Chip Select 2 (again)
+#define AT91_PIO_PSR_PCK2X (1<<31) // Programmable Clock Output 2
+
+//PIO Controller B Peripheral B
+#define AT91_PIO_PSR_NBS0X (1<< 0) // EBI: Address 0 / SDRAM Byte Mask 0
+#define AT91_PIO_PSR_NBS2X (1<< 1) // EBI: Address 1 / SDRAM Byte Mask 2
+#define AT91_PIO_PSR_A2X (1<< 2) // EBI: Address 2
+#define AT91_PIO_PSR_A3X (1<< 3) // EBI: Address 3
+#define AT91_PIO_PSR_A4X (1<< 4) // EBI: Address 4
+#define AT91_PIO_PSR_A5X (1<< 5) // EBI: Address 5
+#define AT91_PIO_PSR_A6X (1<< 6) // EBI: Address 6
+#define AT91_PIO_PSR_A7X (1<< 7) // EBI: Address 7
+#define AT91_PIO_PSR_A8X (1<< 8) // EBI: Address 8
+#define AT91_PIO_PSR_A9X (1<< 9) // EBI: Address 9
+#define AT91_PIO_PSR_A10X (1<<10) // EBI: Address 10
+#define AT91_PIO_PSR_A11X (1<<11) // EBI: Address 11
+#define AT91_PIO_PSR_A12X (1<<12) // EBI: Address 12
+#define AT91_PIO_PSR_A13X (1<<13) // EBI: Address 13
+#define AT91_PIO_PSR_A14X (1<<14) // EBI: Address 14
+#define AT91_PIO_PSR_A15X (1<<15) // EBI: Address 15
+#define AT91_PIO_PSR_BA0X (1<<16) // EBI: Address 16 /
+ // SDRAM Bank Select 0
+#define AT91_PIO_PSR_BA1X (1<<17) // EBI: Address 17 /
+ // SDRAM Bank Select 1
+#define AT91_PIO_PSR_D16 (1<<18) // EBI: Data 16
+#define AT91_PIO_PSR_D17 (1<<19) // EBI: Data 17
+#define AT91_PIO_PSR_D18 (1<<20) // EBI: Data 18
+#define AT91_PIO_PSR_D19 (1<<21) // EBI: Data 19
+#define AT91_PIO_PSR_D20 (1<<22) // EBI: Data 20
+#define AT91_PIO_PSR_D21 (1<<23) // EBI: Data 21
+#define AT91_PIO_PSR_D22 (1<<24) // EBI: Data 22
+#define AT91_PIO_PSR_D23 (1<<25) // EBI: Data 23
+#define AT91_PIO_PSR_D24 (1<<26) // EBI: Data 24
+#define AT91_PIO_PSR_D25 (1<<27) // EBI: Data 25
+#define AT91_PIO_PSR_D26 (1<<28) // EBI: Data 26
+#define AT91_PIO_PSR_D27 (1<<29) // EBI: Data 27
+#define AT91_PIO_PSR_D28 (1<<30) // EBI: Data 28
+#define AT91_PIO_PSR_D29 (1<<31) // EBI: Data 29
+
+//PIO Controller C Peripheral A
+#define AT91_EBI_D0 AT91_PIN(2,0, 0) // EBI: Data 0
+#define AT91_EBI_D1 AT91_PIN(2,0, 1) // EBI: Data 1
+#define AT91_EBI_D2 AT91_PIN(2,0, 2) // EBI: Data 2
+#define AT91_EBI_D3 AT91_PIN(2,0, 3) // EBI: Data 3
+#define AT91_EBI_D4 AT91_PIN(2,0, 4) // EBI: Data 4
+#define AT91_EBI_D5 AT91_PIN(2,0, 5) // EBI: Data 5
+#define AT91_EBI_D6 AT91_PIN(2,0, 6) // EBI: Data 6
+#define AT91_EBI_D7 AT91_PIN(2,0, 7) // EBI: Data 7
+#define AT91_EBI_D8 AT91_PIN(2,0, 8) // EBI: Data 8
+#define AT91_EBI_D9 AT91_PIN(2,0, 9) // EBI: Data 9
+#define AT91_EBI_D10 AT91_PIN(2,0,10) // EBI: Data 10
+#define AT91_EBI_D11 AT91_PIN(2,0,11) // EBI: Data 11
+#define AT91_EBI_D12 AT91_PIN(2,0,12) // EBI: Data 12
+#define AT91_EBI_D13 AT91_PIN(2,0,13) // EBI: Data 13
+#define AT91_EBI_D14 AT91_PIN(2,0,14) // EBI: Data 14
+#define AT91_EBI_D15 AT91_PIN(2,0,15) // EBI: Data 15
+#define AT91_EBI_A18 AT91_PIN(2,0,16) // EBI: Address 18
+#define AT91_EBI_A19 AT91_PIN(2,0,17) // EBI: Address 19
+#define AT91_EBI_A20 AT91_PIN(2,0,18) // EBI: Address 20
+#define AT91_EBI_A21_NANDALE \
+ AT91_PIN(2,0,19) // EBI: Address 21 /
+ // NAND Flash Address Line Enable
+#define AT91_EBI_A22_REG_NANDCLE \
+ AT91_PIN(2,0,20) // EBI: Address 22 /
+ // CompactFlash REG Signal /
+ // NAND Flash Command Line Enable
+#define AT91_EBI_CFNRW AT91_PIN(2,0,23) // EBI: CF Read Not Write Signal
+
+//PIO Controller C Peripheral B
+#define AT91_USART_RTS1X AT91_PIN(2,1, 8) // USART 1 Ready To Send
+#define AT91_USART_DTR1X AT91_PIN(2,1, 9) // USART 1 Data Terminal Ready
+#define AT91_PCK_PCK0X AT91_PIN(2,1,10) // Programmable Clock Output 0
+#define AT91_PCK_PCK1XX AT91_PIN(2,1,11) // Programmable Clock Output 1
+#define AT91_PCK_PCK2XX AT91_PIN(2,1,12) // Programmable Clock Output 2
+#define AT91_SPI_NPCS1XX AT91_PIN(2,1,14) // SPI Chip Select 1
+#define AT91_EBI_NCS3_NANDCS \
+ AT91_PIN(2,1,15) // EBI: Chip Select 3 /
+ // NAND Flash Chip Select
+#define AT91_EBI_NWAIT AT91_PIN(2,1,16) // EBI: External Wait Signal
+#define AT91_EBI_NANDOE AT91_PIN(2,1,17) // EBI: NAND Flash Output Enable
+#define AT91_EBI_NANDWE AT91_PIN(2,1,18) // EBI: NAND Flash Write Enable
+#define AT91_EBI_NCS7 AT91_PIN(2,1,20) // EBI: Chip Select 7
+#define AT91_EBI_NWR0_NWE_CFWE \
+ AT91_PIN(2,1,21) // EBI: Write 0 /
+ // SMC Write Enable /
+ // CompactFlash Write Enable
+#define AT91_EBI_NRD_CFOE AT91_PIN(2,1,22) // EBI: SMC Read Enable /
+ // CompactFlash Output Enable
+#define AT91_EBI_NCS0 AT91_PIN(2,1,23) // EBI: Chip Select 0
+
+//PIO Controller C Peripheral A
+#define AT91_PIO_PSR_D0 (1<< 0) // EBI: Data 0
+#define AT91_PIO_PSR_D1 (1<< 1) // EBI: Data 1
+#define AT91_PIO_PSR_D2 (1<< 2) // EBI: Data 2
+#define AT91_PIO_PSR_D3 (1<< 3) // EBI: Data 3
+#define AT91_PIO_PSR_D4 (1<< 4) // EBI: Data 4
+#define AT91_PIO_PSR_D5 (1<< 5) // EBI: Data 5
+#define AT91_PIO_PSR_D6 (1<< 6) // EBI: Data 6
+#define AT91_PIO_PSR_D7 (1<< 7) // EBI: Data 7
+#define AT91_PIO_PSR_D8 (1<< 8) // EBI: Data 8
+#define AT91_PIO_PSR_D9 (1<< 9) // EBI: Data 9
+#define AT91_PIO_PSR_D10 (1<<10) // EBI: Data 10
+#define AT91_PIO_PSR_D11 (1<<11) // EBI: Data 11
+#define AT91_PIO_PSR_D12 (1<<12) // EBI: Data 12
+#define AT91_PIO_PSR_D13 (1<<13) // EBI: Data 13
+#define AT91_PIO_PSR_D14 (1<<14) // EBI: Data 14
+#define AT91_PIO_PSR_D15 (1<<15) // EBI: Data 15
+#define AT91_PIO_PSR_A18 (1<<16) // EBI: Address 18
+#define AT91_PIO_PSR_A19 (1<<17) // EBI: Address 19
+#define AT91_PIO_PSR_A20 (1<<18) // EBI: Address 20
+#define AT91_PIO_PSR_NANDALE (1<<19) // EBI: Address 21 /
+ // NAND Flash Address Line Enable
+#define AT91_PIO_PSR_NANDCLE (1<<20) // EBI: Address 22 /
+ // CompactFlash REG Signal /
+ // NAND Flash Command Line Enable
+#define AT91_PIO_PSR_CFNRW (1<<23) // EBI: CF Read Not Write Signal
+
+//PIO Controller C Peripheral B
+#define AT91_PIO_PSR_RTS1X (1<< 8) // USART 1 Ready To Send
+#define AT91_PIO_PSR_DTR1X (1<< 9) // USART 1 Data Terminal Ready
+#define AT91_PIO_PSR_PCK0X (1<<10) // Programmable Clock Output 0
+#define AT91_PIO_PSR_PCK1XX (1<<11) // Programmable Clock Output 1
+#define AT91_PIO_PSR_PCK2XX (1<<12) // Programmable Clock Output 2
+#define AT91_PIO_PSR_NPCS1XX (1<<14) // SPI Chip Select 1
+#define AT91_PIO_PSR_NANDCS (1<<15) // EBI: Chip Select 3 /
+ // NAND Flash Chip Select
+#define AT91_PIO_PSR_NWAIT (1<<16) // EBI: External Wait Signal
+#define AT91_PIO_PSR_NANDOE (1<<17) // EBI: NAND Flash Output Enable
+#define AT91_PIO_PSR_NANDWE (1<<18) // EBI: NAND Flash Write Enable
+#define AT91_PIO_PSR_NCS7 (1<<20) // EBI: Chip Select 7
+#define AT91_PIO_PSR_CFWE (1<<21) // EBI: Write 0 / SMC Write Enable /
+ // CompactFlash Write Enable
+#define AT91_PIO_PSR_CFOE (1<<22) // EBI: SMC Read Enable /
+ // CompactFlash Output Enable
+#define AT91_PIO_PSR_NCS0 (1<<23) // EBI: Chip Select 0
+
+#endif // CYGHWR_HAL_ARM_AT91SAM7SE
+
#else
#define AT91_TC_TCLK0 AT91_PIN(0,0, 0) // Timer #0 clock
#define AT91_TC_TIOA0 AT91_PIN(0,0, 1) // Timer #0 signal A
@@ -1043,6 +1472,12 @@
//=============================================================================
// External Bus Interface
+#if defined(CYGHWR_HAL_ARM_AT91_R40807) || \
+ defined(CYGHWR_HAL_ARM_AT91_R40008) || \
+ defined(CYGHWR_HAL_ARM_AT91_M42800A) || \
+ defined(CYGHWR_HAL_ARM_AT91_M55800A)
+
+
#ifndef AT91_EBI
#define AT91_EBI 0xFFE00000
#endif
@@ -1091,6 +1526,73 @@
#define AT91_EBI_MCR_ALE_1M 0x7 // Address line enable
#define AT91_EBI_MCR_DRP (0x1 << 4) // Data read protocol
+#elif defined(CYGHWR_HAL_ARM_AT91SAM7SE)
+
+#ifndef AT91_EBI
+#define AT91_EBI 0xFFFFFF80
+#endif
+
+#define AT91_EBI_CSA 0x00
+#define AT91_EBI_CSA_CS1A (1 << 1) // Assign NCS1 to SDRAM instead of
+ // static memory
+#define AT91_EBI_CSA_CS2A (1 << 2) // Assign NCS2 (as second slot CS),
+ // NCS5, NCS6 to CompactFlash (access of
+ // NCS5, NCS6 areas are undefined)
+ // instead of static memory
+#define AT91_EBI_CSA_CS3A (1 << 3) // Assign NCS3 to NAND Flash instead of
+ // static memory
+#define AT91_EBI_CSA_CS4A (1 << 4) // Assign NCS4 (as second slot CS), NCS5,
+ // NCS6 to CompactFlash (access of NCS5,
+ // NCS6 areas are undefined) instead of
+ // static memory
+#define AT91_EBI_CSA_NWPC (1 << 16) // Enable SMC NWAIT pin
+
+#define AT91_EBI_SMC 0x90 // SMC Configuration Registers
+#define AT91_EBI_SMC_CSR(n) (AT91_EBI_SMC+0x4*(n)) // Chip select registers
+#define AT91_EBI_SMC_CSR_NWS_MASK (0x7F << 0) // Number of Wait States mask
+#define AT91_EBI_SMC_CSR_NWS(n) \
+ ( ((n)<< 0) & AT91_EBI_SMC_CSR_NWS_MASK ) // Number of Wait States
+ // (depends on read protocol)
+#define AT91_EBI_SMC_CSR_WSEN (1 << 7) // Wait State Enable
+#define AT91_EBI_SMC_CSR_TDF_MASK (0x0F << 8) // Data Float Time mask
+#define AT91_EBI_SMC_CSR_TDF(n) \
+ ( ((n)<< 8) & AT91_EBI_SMC_CSR_TDF_MASK ) // Data Float Time (between
+ // different chip selects)
+#define AT91_EBI_SMC_CSR_BAT_2x8 (0 << 7) // Byte Access Type
+ // (two 8-bit wide devices)
+#define AT91_EBI_SMC_CSR_BAT_1x16 (1 << 7) // Byte Access Type
+ // (one 16-bit wide device)
+#define AT91_EBI_SMC_CSR_DBW_MASK (0x03 << 13) // Data Bus Width mask
+#define AT91_EBI_SMC_CSR_DBW_16 (0x01 << 13) // Data Bus Width: 16 bit
+#define AT91_EBI_SMC_CSR_DBW_8 (0x02 << 13) // Data Bus Width: 8 bit
+#define AT91_EBI_SMC_CSR_DRP_STD (0x00 << 15) // Data Read Protocol: standard
+#define AT91_EBI_SMC_CSR_DRP_EARLY (0x01 << 15) // Data Read Protocol: early
+#define AT91_EBI_SMC_CSR_ACSS_MASK (0x03 << 16) // Address to Chip Select
+ // Setup mask
+#define AT91_EBI_SMC_CSR_ACSS(n) \
+ ( ((n)<< 16) & AT91_EBI_SMC_CSR_ACSS_MASK ) // Address to Chip Select
+ // Setup: hold address before
+ // and after CS for n cycles
+#define AT91_EBI_SMC_CSR_RWSETUP_MASK \
+ (0x07 << 24) // Read and Write Signal
+ // Setup Time
+#define AT91_EBI_SMC_CSR_RWSETUP(n) \
+ ( ((n)<< 24) & AT91_EBI_SMC_CSR_RWSETUP_MASK )// Read and Write Signal
+ // Setup Time is (n+0.5)
+ // (there are exceptions)
+#define AT91_EBI_SMC_CSR_RWHOLD_MASK \
+ (0x07 << 28) // Read and Write Signal
+ // Hold Time
+#define AT91_EBI_SMC_CSR_RWHOLD(n) \
+ ( ((n)<< 28) & AT91_EBI_SMC_CSR_RWHOLD_MASK ) // Read and Write Signal Hold
+ // Time is n (there are
+ // exceptions)
+
+#define AT91_MC_SDRAMC 0xB0 // SDRAMC Configuration Registers
+#define AT91_MC_ECC 0xDC // ECC Configuration Registers
+#endif
+
+
//=============================================================================
// Power Saving or Management
@@ -1298,6 +1800,30 @@
#define AT91_PMC_PCER_CAN (1 <<15) // Controller Area Network
#define AT91_PMC_PCER_EMAC (1 <<16) // Ethernet MAC
#define AT91_PMC_PCER_ADC (1 <<17) // Analog-to-Digital Converter
+
+#elif defined(CYGHWR_HAL_ARM_AT91SAM7SE)
+#define AT91_PMC_SCER_PCK (1 << 0) // Processor Clock
+#define AT91_PMC_SCER_UDP (1 << 7) // USB Device Clock
+#define AT91_PMC_SCER_PCK0 (1 << 8) // Programmable Clock Output
+#define AT91_PMC_SCER_PCK1 (1 << 9) // Programmable Clock Output
+#define AT91_PMC_SCER_PCK2 (1 << 10) // Programmable Clock Output
+#define AT91_PMC_SCER_PCK3 (1 << 11) // Programmable Clock Output
+
+#define AT91_PMC_PCER_PIOA (1 << 2) // Parallel IO Controller
+#define AT91_PMC_PCER_PIOB (1 << 3) // Parallel IO Controller
+#define AT91_PMC_PCER_PIOC (1 << 4) // Parallel IO Controller
+#define AT91_PMC_PCER_SPI (1 << 5) // Serial Peripheral Interface
+#define AT91_PMC_PCER_US0 (1 << 6) // USART 0
+#define AT91_PMC_PCER_US1 (1 << 7) // USART 1
+#define AT91_PMC_PCER_SSC (1 << 8) // Serial Synchronous Controller
+#define AT91_PMC_PCER_TWI (1 << 9) // Two-Wire Interface
+#define AT91_PMC_PCER_PWMC (1 <<10) // PWM Controller
+#define AT91_PMC_PCER_UDP (1 <<11) // USB Device Port
+#define AT91_PMC_PCER_TC0 (1 <<12) // Timer Counter 0
+#define AT91_PMC_PCER_TC1 (1 <<13) // Timer Counter 1
+#define AT91_PMC_PCER_TC2 (1 <<14) // Timer Counter 2
+#define AT91_PMC_PCER_ADC (1 <<15) // Analog-to-Digital Converter
+
#else // Something unknown
#error Unknown AT91 variant
@@ -1486,7 +2012,9 @@
#define AT91_MC_FMR_3FWS (3 << 8) // 4R,4W wait states
#define AT91_MC_FMR_FMCN_MASK (0xff << 16)
#define AT91_MC_FMR_FMCN_SHIFT 16
+#ifndef AT91_MC_FCR
#define AT91_MC_FCR 0x64 // Flash Command Register
+#endif
#define AT91_MC_FCR_START_PROG (0x1 << 0) // Start Programming of Page
#define AT91_MC_FCR_LOCK (0x2 << 0) // Lock sector
#define AT91_MC_FCR_PROG_LOCK (0x3 << 0) // Program and Lock
@@ -1498,7 +2026,9 @@
#define AT91_MC_FCR_PAGE_MASK (0x3ff)
#define AT91_MC_FCR_PAGE_SHIFT 8
#define AT91_MC_FCR_KEY (0x5a << 24) // Key to enable command
+#ifndef AT91_MC_FSR
#define AT91_MC_FSR 0x68 // Flash Status Register
+#endif
#define AT91_MC_FSR_FRDY (1 << 0) // Flash Ready for next command
#define AT91_MC_FSR_LOCKE (1 << 2) // Programming of a locked block
#define AT91_MC_FSR_PROGE (1 << 3) // Programming error
@@ -1507,6 +2037,51 @@
#define AT91_MC_FSR_GPNVM1 (1 << 9) // General purpose NVM bit 1
#endif
+#if defined(CYGHWR_HAL_ARM_AT91SAM7SE)
+#define AT91_MC_PUIA(n) (0x10+(n)*4) // MC Protection Unit Area n
+#define AT91_MC_PUIA_PROT_MASK (0x3 << 0) // Protection mask
+#define AT91_MC_PUIA_PROT_PNAUNA (0x0 << 0) // No Access, User=No Access
+#define AT91_MC_PUIA_PROT_PRWUNA (0x1 << 0) // Privilige=R/W, User=No Access
+#define AT91_MC_PUIA_PROT_PRWURO (0x2 << 0) // Privilige=R/W, User=R Only
+#define AT91_MC_PUIA_PROT_PRWURW (0x3 << 0) // Privilige=R/W, User=R/W
+#define AT91_MC_PUIA_SIZE_MASK (0xF << 4) // Area Size mask
+#define AT91_MC_PUIA_SIZE_1KB (0x0 << 4) // Area Size=1KB
+#define AT91_MC_PUIA_SIZE_2KB (0x1 << 4) // Area Size=2KB
+#define AT91_MC_PUIA_SIZE_4KB (0x2 << 4) // Area Size=4KB
+#define AT91_MC_PUIA_SIZE_8KB (0x3 << 4) // Area Size=8KB
+#define AT91_MC_PUIA_SIZE_16KB (0x4 << 4) // Area Size=16KB
+#define AT91_MC_PUIA_SIZE_32KB (0x5 << 4) // Area Size=32KB
+#define AT91_MC_PUIA_SIZE_64KB (0x6 << 4) // Area Size=64KB
+#define AT91_MC_PUIA_SIZE_128KB (0x7 << 4) // Area Size=128KB
+#define AT91_MC_PUIA_SIZE_256KB (0x8 << 4) // Area Size=256KB
+#define AT91_MC_PUIA_SIZE_512KB (0x9 << 4) // Area Size=512KB
+#define AT91_MC_PUIA_SIZE_1MB (0xA << 4) // Area Size=1MB
+#define AT91_MC_PUIA_SIZE_2MB (0xB << 4) // Area Size=2MB
+// Datasheet says value is 0xD, but it's out of the sequence and
+// Atmel header also says 0xC.
+#define AT91_MC_PUIA_SIZE_4MB (0xC << 4) // Area Size=4MB
+// The following are not mentioned in datasheet, but present in Atmel header
+#define AT91_MC_PUIA_SIZE_8MB (0xD << 4) // Area Size=8MByte
+#define AT91_MC_PUIA_SIZE_16MB (0xE << 4) // Area Size=16MByte
+#define AT91_MC_PUIA_SIZE_64MB (0xF << 4) // Area Size=64MByte
+#define AT91_MC_BA_MASK (0x3FFFF << 10) // Area Base Address Mask
+#define AT91_MC_BA(addr) ((addr) << 10) // Set Area Base Address in
+ // multiples of 1KB (must be
+ // a multiple of the selected
+ // Area Size)
+#define AT91_MC_PUP 0x50 // MC Protection Unit Peripherals
+#define AT91_MC_PUP_PROT_MASK (0x3 << 0) // Protection mask
+#define AT91_MC_PUP_PROT_PNAUNA (0x0 << 0) // Privilige=No Access,
+ // User=No Access (DO NOT USE)
+#define AT91_MC_PUP_PROT_PRWUNA (0x1 << 0) // Privilige=R/W, User=No Access
+#define AT91_MC_PUP_PROT_PRWURO (0x2 << 0) // Privilige=R/W, User=R Only
+#define AT91_MC_PUP_PROT_PRWURW (0x3 << 0) // Privilige=R/W, User=R/W
+#define AT91_MC_PUER 0x54 // Protection Unit Enable Register
+#define AT91_MC_PUER_PUEB (0x1) // Protection Unit Enable Bit
+ // (PROGRAM ALL AREA REGISTERS BEFORE
+ // ENABLE)
+#endif
+
//=============================================================================
// Debug Unit
@@ -2306,6 +2881,7 @@
#define AT91_PWM_CH2 0xFFFCC240
#define AT91_PWM_CH3 0xFFFCC260
#define AT91_PWM_CH_SIZE 0x20
+#define AT91_PWM_CH(n) (AT91_PWM_CH0+(n)*AT91_PWM_CH_SIZE)
#endif
#if defined(CYGHWR_HAL_ARM_AT91SAM7)
@@ -2383,6 +2959,7 @@
#define AT91_PWM_CCNTR (0x0C) // Channel Counter
#define AT91_PWM_CUPDR (0x10) // Channel Update
+
#endif
//=============================================================================
@@ -2511,7 +3088,9 @@
#define AT91_PIN_INTERRUPT_DISABLE 0
#ifndef AT91_PIOB
+//------------------------
// Only one PIO controller
+//------------------------
// Configure a peripheral pin for peripheral operation
#define HAL_ARM_AT91_PIO_CFG(_pin_) \
@@ -2555,14 +3134,70 @@
HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 0, AT91_PIO); \
CYG_MACRO_END
-#else // !AT91_PIOB
+#elif !defined(AT91_PIOC) // !AT91_PIOB
+//--------------------
// Two PIO controllers
+//--------------------
// Configure a peripheral pin for peripheral operation
-#define HAL_ARM_AT91_PIO_CFG(_pin_) \
- CYG_MACRO_START \
+#define HAL_ARM_AT91_PIO_CFG(_pin_) \
+ CYG_MACRO_START \
+ HAL_ARM_AT91_PIOX_CFG(_pin_, 0, AT91_PIO); \
+ HAL_ARM_AT91_PIOX_CFG(_pin_, 1, AT91_PIOB); \
+ CYG_MACRO_END
+
+// Configure a GPIO pin direction
+#define HAL_ARM_AT91_GPIO_CFG_DIRECTION(_pin_, _dir_) \
+ CYG_MACRO_START \
+ HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, 0, AT91_PIO); \
+ HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, 1, AT91_PIOB); \
+ CYG_MACRO_END
+
+// Configure a GPIO pin pullup resistor
+#define HAL_ARM_AT91_GPIO_CFG_PULLUP(_pin_, _enable_) \
+ CYG_MACRO_START \
+ HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, 0, AT91_PIO); \
+ HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, 1, AT91_PIOB); \
+ CYG_MACRO_END
+
+// Configure a GPIO pin to generate interrupts
+#define HAL_ARM_AT91_GPIO_CFG_INTERRUPT(_pin_, _enable_) \
+ CYG_MACRO_START \
+ HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, 0, AT91_PIO); \
+ HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, 1, AT91_PIOB); \
+ CYG_MACRO_END
+
+// Set a GPIO pin to 1
+#define HAL_ARM_AT91_GPIO_SET(_pin_) \
+ CYG_MACRO_START \
+ HAL_ARM_AT91_GPIOX_SET(_pin_, 0, AT91_PIO); \
+ HAL_ARM_AT91_GPIOX_SET(_pin_, 1, AT91_PIOB); \
+ CYG_MACRO_END
+
+// Reset a GPIO pin to 0
+#define HAL_ARM_AT91_GPIO_RESET(_pin_) \
+ CYG_MACRO_START \
+ HAL_ARM_AT91_GPIOX_RESET(_pin_, 0, AT91_PIO); \
+ HAL_ARM_AT91_GPIOX_RESET(_pin_, 1, AT91_PIOB); \
+ CYG_MACRO_END
+
+// Get the state of a GPIO pin
+#define HAL_ARM_AT91_GPIO_GET(_pin_, _value_) \
+ CYG_MACRO_START \
+ HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 0, AT91_PIO); \
+ HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 1, AT91_PIOB); \
+ CYG_MACRO_END
+#else
+//----------------------
+// Three PIO controllers
+//----------------------
+
+// Configure a peripheral pin for peripheral operation
+#define HAL_ARM_AT91_PIO_CFG(_pin_) \
+ CYG_MACRO_START \
HAL_ARM_AT91_PIOX_CFG(_pin_, 0, AT91_PIO); \
HAL_ARM_AT91_PIOX_CFG(_pin_, 1, AT91_PIOB); \
+ HAL_ARM_AT91_PIOX_CFG(_pin_, 2, AT91_PIOC); \
CYG_MACRO_END
// Configure a GPIO pin direction
@@ -2570,6 +3205,7 @@
CYG_MACRO_START \
HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, 0, AT91_PIO); \
HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, 1, AT91_PIOB); \
+ HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, 2, AT91_PIOC); \
CYG_MACRO_END
// Configure a GPIO pin pullup resistor
@@ -2577,6 +3213,7 @@
CYG_MACRO_START \
HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, 0, AT91_PIO); \
HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, 1, AT91_PIOB); \
+ HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, 2, AT91_PIOC); \
CYG_MACRO_END
// Configure a GPIO pin to generate interrupts
@@ -2584,6 +3221,7 @@
CYG_MACRO_START \
HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, 0, AT91_PIO); \
HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, 1, AT91_PIOB); \
+ HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, 2, AT91_PIOC); \
CYG_MACRO_END
// Set a GPIO pin to 1
@@ -2591,6 +3229,7 @@
CYG_MACRO_START \
HAL_ARM_AT91_GPIOX_SET(_pin_, 0, AT91_PIO); \
HAL_ARM_AT91_GPIOX_SET(_pin_, 1, AT91_PIOB); \
+ HAL_ARM_AT91_GPIOX_SET(_pin_, 2, AT91_PIOC); \
CYG_MACRO_END
// Reset a GPIO pin to 0
@@ -2598,6 +3237,7 @@
CYG_MACRO_START \
HAL_ARM_AT91_GPIOX_RESET(_pin_, 0, AT91_PIO); \
HAL_ARM_AT91_GPIOX_RESET(_pin_, 1, AT91_PIOB); \
+ HAL_ARM_AT91_GPIOX_RESET(_pin_, 2, AT91_PIOC); \
CYG_MACRO_END
// Get the state of a GPIO pin
@@ -2605,6 +3245,7 @@
CYG_MACRO_START \
HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 0, AT91_PIO); \
HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 1, AT91_PIOB); \
+ HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 2, AT91_PIOC); \
CYG_MACRO_END
#endif //!AT91_PIOB
Index: io/usb/serial/slave/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/io/usb/serial/slave/current/ChangeLog,v
retrieving revision 1.2
diff -u -r1.2 ChangeLog
--- io/usb/serial/slave/current/ChangeLog 14 Aug 2008 19:02:51 -0000 1.2
+++ io/usb/serial/slave/current/ChangeLog 3 Nov 2008 08:38:43 -0000
@@ -1,3 +1,10 @@
+2008-11-03 Gabor Toeroek <tgabor84@gmail.com>
+
+ * cdl/usbs_serial.cdl:
+ * src/usbs_serial.c (usb_configuration): Add to enumeration if the
+ device is bus powered or self powered, and what power it will
+ draw.
+
2008-08-09 Frank Pagliughi <fpagliughi@mindspring.com>
* host/linux/ecos_usbserial.c (ecos_usbserial_probe): fix compiling
Index: io/usb/serial/slave/current/cdl/usbs_serial.cdl
===================================================================
RCS file: /cvs/ecos/ecos/packages/io/usb/serial/slave/current/cdl/usbs_serial.cdl,v
retrieving revision 1.1
diff -u -r1.1 usbs_serial.cdl
--- io/usb/serial/slave/current/cdl/usbs_serial.cdl 12 Jul 2008 10:30:34 -0000 1.1
+++ io/usb/serial/slave/current/cdl/usbs_serial.cdl 3 Nov 2008 08:38:43 -0000
@@ -191,6 +191,32 @@
is first plugged into the host."
}
+ cdl_option CYGOPT_IO_USB_SLAVE_SERIAL_BUSPOWERED {
+ display "The Device is bus powered"
+ default_value 0
+ flavor bool
+ description "
+ Tells the host whether the Device is a bus powered
+ device or a self powered device."
+ }
+ cdl_option CYGNUM_IO_USB_SLAVE_SERIAL_CURRENTDRAW {
+ display "Maximum current (in mA) drawn from USB bus"
+ flavor data
+ default_value 100
+ legal_values 1 to 500
+ requires { (CYGNUM_IO_USB_SLAVE_SERIAL_CURRENTDRAW > 100)
+ implies CYGBLD_IO_USB_SLAVE_SERIAL_BUSPOWERED }
+ description "
+ The maximum current drawn by the Device from the USB bus.
+ It should report the peak value. A self powered device
+ can draw up to 100mA, a bus powered device can draw up to
+ 500mA. (If it is sometimes below 100mA and sometimes over,
+ then a tranition could be done at runtime between self and
+ bus powered modes, but that would be complicated and the
+ device would have to return from configured to addressed
+ state. For details, see the USB specification.)"
+ }
+
cdl_option CYGBLD_IO_USB_SLAVE_SERIAL_DEBUG {
display "Enable debug output from the driver"
default_value 0
Index: io/usb/serial/slave/current/src/usbs_serial.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/io/usb/serial/slave/current/src/usbs_serial.c,v
retrieving revision 1.1
diff -u -r1.1 usbs_serial.c
--- io/usb/serial/slave/current/src/usbs_serial.c 12 Jul 2008 10:30:34 -0000 1.1
+++ io/usb/serial/slave/current/src/usbs_serial.c 3 Nov 2008 08:38:43 -0000
@@ -126,9 +126,13 @@
number_interfaces: USBS_SERIAL_NUM_IFACE,
configuration_id: 1,
configuration_str: 0,
+#ifdef CYGOPT_IO_USB_SLAVE_SERIAL_BUSPOWERED
+ attributes: (USB_CONFIGURATION_DESCRIPTOR_ATTR_REQUIRED),
+#else
attributes: (USB_CONFIGURATION_DESCRIPTOR_ATTR_REQUIRED |
USB_CONFIGURATION_DESCRIPTOR_ATTR_SELF_POWERED),
- max_power: 50
+#endif
+ max_power: (CYGNUM_IO_USB_SLAVE_SERIAL_CURRENTDRAW+1)/2
};
// ----- Interface Descriptor -----