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ECOS Cortex-M STM32 wallclock driver
- From: "simon dot kallweit at intefo dot ch" <simon dot kallweit at intefo dot ch>
- To: ecos-patches at ecos dot sourceware dot org
- Date: Thu, 06 Nov 2008 11:50:07 +0100
- Subject: ECOS Cortex-M STM32 wallclock driver
As promised, here a first version of a STM32 wallclock driver, tested in
all clock configurations. I will implement more features in the future,
things like preserving the RTC on reset, setting alarms etc. But for now
this works great as a normal wallclock.
Simon
diff -r c7133bab1df6 packages/devs/wallclock/cortexm/stm32/current/ChangeLog
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/packages/devs/wallclock/cortexm/stm32/current/ChangeLog Thu Nov 06 11:48:27 2008 +0100
@@ -0,0 +1,43 @@
+2008-11-05 Simon Kallweit <simon.kalweit@intefo.ch>
+
+ * cdl/wallclock_stm32.cdl:
+ * src/stm32_wallclock.cxx:
+ Adapted to ecoscentric cortexm port.
+
+2008-10-27 Simon Kallweit <simon.kallweit@intefo.ch>
+
+ * cdl/stm32_wallclock.cdl:
+ * src/stm32_wallclock.cxx:
+ Driver for on-chip RTC unit.
+
+//===========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
diff -r c7133bab1df6 packages/devs/wallclock/cortexm/stm32/current/cdl/wallclock_stm32.cdl
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/packages/devs/wallclock/cortexm/stm32/current/cdl/wallclock_stm32.cdl Thu Nov 06 11:48:27 2008 +0100
@@ -0,0 +1,77 @@
+# ====================================================================
+#
+# wallclock_stm32.cdl
+#
+# Hardware support for STM32 on-chip RTC.
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 2008 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): Simon Kallweit
+# Contributors:
+# Date: 2008-10-27
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_WALLCLOCK_STM32 {
+ display "STM32 RTC wallclock support"
+ description "
+ Wallclock support for on-chip RTC on STM32 devices.driver for the
+ STM32 controller and compatibles"
+
+ parent CYGPKG_IO_WALLCLOCK
+ active_if CYGPKG_IO_WALLCLOCK
+ active_if CYGPKG_HAL_CORTEXM_STM32
+
+ compile stm32_wallclock.cxx
+
+ implements CYGINT_WALLCLOCK_HW_IMPLEMENTATIONS
+ active_if CYGIMP_WALLCLOCK_HARDWARE
+ implements CYGINT_WALLCLOCK_SET_GET_MODE_SUPPORTED
+
+ cdl_option CYGIMP_WALLCLOCK_HARDWARE {
+ parent CYGPKG_IO_WALLCLOCK_IMPLEMENTATION
+ display "Hardware wallclock"
+ default_value 1
+ implements CYGINT_WALLCLOCK_IMPLEMENTATIONS
+ }
+
+ cdl_option CYGHWR_DEVS_WALLCLOCK_STM32_RTC_SOURCE {
+ display "RTC clock source"
+ flavor data
+ default_value { "LSE" }
+ legal_values { "LSE" "LSI" "HSE_128" }
+ }
+}
diff -r c7133bab1df6 packages/devs/wallclock/cortexm/stm32/current/src/stm32_wallclock.cxx
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/packages/devs/wallclock/cortexm/stm32/current/src/stm32_wallclock.cxx Thu Nov 06 11:48:27 2008 +0100
@@ -0,0 +1,244 @@
+//==========================================================================
+//
+// stm32_wallclock.cxx
+//
+// Wallclock implementation for STM32
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Simon Kallweit
+// Contributors:
+// Date: 2008-10-27
+// Purpose: Wallclock driver for STM32
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_stm32.h>
+#include <pkgconf/wallclock.h>
+#include <pkgconf/devs_wallclock_stm32.h>
+
+#include <cyg/hal/hal_io.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/io/wallclock.hxx>
+
+//==========================================================================
+// Clock Initialization values
+
+#if defined(CYGHWR_DEVS_WALLCLOCK_STM32_RTC_SOURCE_LSE)
+# define CYGHWR_DEVS_WALLCLOCK_STM32_RTCSEL CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_LSE
+# define CYGHWR_DEVS_WALLCLOCK_STM32_CLOCK 32768
+#elif defined(CYGHWR_DEVS_WALLCLOCK_STM32_RTC_SOURCE_LSI)
+# define CYGHWR_DEVS_WALLCLOCK_STM32_RTCSEL CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_LSI
+# define CYGHWR_DEVS_WALLCLOCK_STM32_CLOCK 40000
+#elif defined(CYGHWR_DEVS_WALLCLOCK_STM32_RTC_SOURCE_HSE_128)
+# define CYGHWR_DEVS_WALLCLOCK_STM32_RTCSEL CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_HSE
+# define CYGHWR_DEVS_WALLCLOCK_STM32_CLOCK (CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK / 128)
+#endif
+
+// Wait for registers to be synchronized
+static void
+wait_sync(void)
+{
+ CYG_ADDRESS rtc = CYGHWR_HAL_STM32_RTC;
+ cyg_uint16 crl;
+
+ do
+ {
+ HAL_READ_UINT16( rtc+CYGHWR_HAL_STM32_RTC_CRL, crl );
+ } while ( !(crl & CYGHWR_HAL_STM32_RTC_CRL_RSF) );
+}
+
+// Wait for last write operation to finish
+static void
+wait_rtoff(void)
+{
+ CYG_ADDRESS rtc = CYGHWR_HAL_STM32_RTC;
+ cyg_uint16 crl;
+
+ do
+ {
+ HAL_READ_UINT16( rtc+CYGHWR_HAL_STM32_RTC_CRL, crl );
+ } while ( !(crl & CYGHWR_HAL_STM32_RTC_CRL_RTOFF) );
+}
+
+// Enter/leave configuration mode
+static void
+config_mode(int val)
+{
+ CYG_ADDRESS rtc = CYGHWR_HAL_STM32_RTC;
+ cyg_uint16 crl;
+
+ if (val)
+ wait_rtoff();
+
+ HAL_READ_UINT16( rtc+CYGHWR_HAL_STM32_RTC_CRL, crl );
+ if (val)
+ crl |= CYGHWR_HAL_STM32_RTC_CRL_CNF;
+ else
+ crl &= ~CYGHWR_HAL_STM32_RTC_CRL_CNF;
+ HAL_WRITE_UINT16( rtc+CYGHWR_HAL_STM32_RTC_CRL, crl );
+
+ if (!val)
+ wait_rtoff();
+}
+
+void
+Cyg_WallClock::init_hw_seconds(void)
+{
+ CYG_ADDRESS rcc = CYGHWR_HAL_STM32_RCC;
+ CYG_ADDRESS rtc = CYGHWR_HAL_STM32_RTC;
+ cyg_uint32 bdcr, csr;
+ cyg_uint32 prescaler = CYGHWR_DEVS_WALLCLOCK_STM32_CLOCK - 1;
+
+ // Reset the backup domain if clock source does not match as
+ // RTCSEL can only be written to backup domain once
+ HAL_READ_UINT32( rcc+CYGHWR_HAL_STM32_RCC_BDCR, bdcr );
+ if ((bdcr & CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_XXX) !=
+ CYGHWR_DEVS_WALLCLOCK_STM32_RTCSEL)
+ {
+ // Reset backup domain
+ CYGHWR_HAL_STM32_BD_RESET();
+ }
+
+ // Disable backup domain protection
+ CYGHWR_HAL_STM32_BD_UNPROTECT(1);
+
+#if defined(CYGHWR_DEVS_WALLCLOCK_STM32_RTC_SOURCE_LSI)
+ // Start up LSI clock
+ HAL_READ_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CSR, csr );
+ csr |= CYGHWR_HAL_STM32_RCC_CSR_LSION;
+ HAL_WRITE_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CSR, csr );
+
+ // Wait for LSI clock to startup
+ do
+ {
+ HAL_READ_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CSR, csr );
+ } while( !(csr & CYGHWR_HAL_STM32_RCC_CSR_LSIRDY) );
+#endif
+
+#if defined(CYGHWR_DEVS_WALLCLOCK_STM32_RTC_SOURCE_LSE)
+ // Start up LSE clock
+ HAL_WRITE_UINT32( rcc+CYGHWR_HAL_STM32_RCC_BDCR, CYGHWR_HAL_STM32_RCC_BDCR_LSEON );
+
+ // Wait for LSE clock to startup
+ do
+ {
+ HAL_READ_UINT32( rcc+CYGHWR_HAL_STM32_RCC_BDCR, bdcr );
+ } while( !(bdcr & CYGHWR_HAL_STM32_RCC_BDCR_LSERDY) );
+#endif
+
+ // Enable RTC
+ HAL_READ_UINT32( rcc+CYGHWR_HAL_STM32_RCC_BDCR, bdcr );
+ bdcr |= CYGHWR_DEVS_WALLCLOCK_STM32_RTCSEL;
+ bdcr |= CYGHWR_HAL_STM32_RCC_BDCR_RTCEN;
+ HAL_WRITE_UINT32( rcc+CYGHWR_HAL_STM32_RCC_BDCR, bdcr );
+
+ // Synchronize registers
+ wait_sync();
+
+ // Enter configuration mode
+ config_mode(1);
+
+ // Disable all interrupts
+ HAL_WRITE_UINT16( rtc+CYGHWR_HAL_STM32_RTC_CRH, 0 );
+
+ // Set prescaler load value
+ HAL_WRITE_UINT16( rtc+CYGHWR_HAL_STM32_RTC_PRLL, prescaler & 0xffff);
+ HAL_WRITE_UINT16( rtc+CYGHWR_HAL_STM32_RTC_PRLH, prescaler >> 16);
+
+ // Reset alarm value
+ HAL_WRITE_UINT16( rtc+CYGHWR_HAL_STM32_RTC_ALRL, 0 );
+ HAL_WRITE_UINT16( rtc+CYGHWR_HAL_STM32_RTC_ALRH, 0 );
+
+#ifndef CYGSEM_WALLCLOCK_SET_GET_MODE
+ // Reset counter value
+ HAL_WRITE_UINT16( rtc+CYGHWR_HAL_STM32_RTC_CNTL, 0 );
+ HAL_WRITE_UINT16( rtc+CYGHWR_HAL_STM32_RTC_CNTH, 0 );
+#endif
+
+ // Leave configuration mode
+ config_mode(0);
+
+ // Restore backup domain protection
+ CYGHWR_HAL_STM32_BD_UNPROTECT(0);
+}
+
+cyg_uint32
+Cyg_WallClock::get_hw_seconds(void)
+{
+ CYG_ADDRESS rtc = CYGHWR_HAL_STM32_RTC;
+ cyg_uint16 cnt;
+ cyg_uint32 secs;
+
+ // Synchronize registers
+ wait_sync();
+
+ // Read counter value
+ HAL_READ_UINT16( rtc+CYGHWR_HAL_STM32_RTC_CNTL, cnt );
+ secs = cnt;
+ HAL_READ_UINT16( rtc+CYGHWR_HAL_STM32_RTC_CNTH, cnt );
+ secs |= (cnt << 16);
+
+ return secs;
+}
+
+#ifdef CYGSEM_WALLCLOCK_SET_GET_MODE
+void
+Cyg_WallClock::set_hw_seconds(cyg_uint32 secs)
+{
+ CYG_ADDRESS rtc = CYGHWR_HAL_STM32_RTC;
+
+ // Disable backup domain protection
+ CYGHWR_HAL_STM32_BD_UNPROTECT(1);
+
+ // Enter configuration mode
+ config_mode(1);
+
+ // Set counter value
+ HAL_WRITE_UINT16( rtc+CYGHWR_HAL_STM32_RTC_CNTL, secs & 0xffff );
+ HAL_WRITE_UINT16( rtc+CYGHWR_HAL_STM32_RTC_CNTH, secs >> 16 );
+
+ // Leave configuration mode
+ config_mode(0);
+
+ // Restore backup domain protection
+ CYGHWR_HAL_STM32_BD_UNPROTECT(0);
+}
+#endif
diff -r c7133bab1df6 packages/ecos.db
--- a/packages/ecos.db Thu Nov 06 11:46:59 2008 +0100
+++ b/packages/ecos.db Thu Nov 06 11:48:27 2008 +0100
@@ -6787,13 +6787,23 @@
}
package CYGPKG_DEVS_FLASH_STM32 {
- alias { "Internal FLASH memory support for ST STM32" flash_stm32 }
- directory devs/flash/cortexm/stm32
- script flash_stm32.cdl
- hardware
+ alias { "Internal FLASH memory support for ST STM32" flash_stm32 }
+ directory devs/flash/cortexm/stm32
+ script flash_stm32.cdl
+ hardware
description "
This package contains hardware support for the internal FLASH memory
- on the ST STM32 devices."
+ on the ST STM32 devices."
+}
+
+package CYGPKG_DEVS_WALLCLOCK_STM32 {
+ alias { "ST STM32 RTC wallclock support" wallclock_stm32 }
+ directory devs/wallclock/cortexm/stm32
+ script wallclock_stm32.cdl
+ hardware
+ description "
+ Wallclock support for on-chip RTC on STM32 devices.driver for the
+ STM32 controller and compatibles"
}
target stm3210e_eval {
@@ -6804,6 +6814,7 @@
CYGPKG_DEVS_FLASH_AMD_AM29XXXXX_V2
CYGPKG_DEVS_FLASH_STM32
CYGPKG_IO_SERIAL_CORTEXM_STM32
+ CYGPKG_DEVS_WALLCLOCK_STM32
}
description "The stm3210e_eval target provides the packages needed
to run eCos on the STM3210E EVAL board."
diff -r c7133bab1df6 packages/hal/cortexm/stm32/var/current/include/var_io.h
--- a/packages/hal/cortexm/stm32/var/current/include/var_io.h Thu Nov 06 11:46:59 2008 +0100
+++ b/packages/hal/cortexm/stm32/var/current/include/var_io.h Thu Nov 06 11:48:27 2008 +0100
@@ -242,6 +242,45 @@
#define CYGHWR_HAL_STM32_RCC_CSR_WWDGRSTF BIT_(30)
#define CYGHWR_HAL_STM32_RCC_CSR_LPWRRSTF BIT_(31)
+#define CYGHWR_HAL_STM32_RCC_BDCR_LSEON BIT_(0)
+#define CYGHWR_HAL_STM32_RCC_BDCR_LSERDY BIT_(1)
+#define CYGHWR_HAL_STM32_RCC_BDCR_LSEBYP BIT_(2)
+#define CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_NO VALUE_(8,0)
+#define CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_LSE VALUE_(8,1)
+#define CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_LSI VALUE_(8,2)
+#define CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_HSE VALUE_(8,3)
+#define CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_XXX VALUE_(8,3)
+#define CYGHWR_HAL_STM32_RCC_BDCR_RTCEN BIT_(15)
+#define CYGHWR_HAL_STM32_RCC_BDCR_BDRST BIT_(16)
+
+//=============================================================================
+// Realtime Clock
+
+#define CYGHWR_HAL_STM32_RTC_CRH 0x00
+#define CYGHWR_HAL_STM32_RTC_CRL 0x04
+#define CYGHWR_HAL_STM32_RTC_PRLH 0x08
+#define CYGHWR_HAL_STM32_RTC_PRLL 0x0C
+#define CYGHWR_HAL_STM32_RTC_DIVH 0x10
+#define CYGHWR_HAL_STM32_RTC_DIVL 0x14
+#define CYGHWR_HAL_STM32_RTC_CNTH 0x18
+#define CYGHWR_HAL_STM32_RTC_CNTL 0x1C
+#define CYGHWR_HAL_STM32_RTC_ALRH 0x20
+#define CYGHWR_HAL_STM32_RTC_ALRL 0x24
+
+// CRH fields
+
+#define CYGHWR_HAL_STM32_RTC_CRH_SECIE BIT_(0)
+#define CYGHWR_HAL_STM32_RTC_CRH_ALRIE BIT_(1)
+#define CYGHWR_HAL_STM32_RTC_CRH_OWIE BIT_(2)
+
+// CRL fields
+
+#define CYGHWR_HAL_STM32_RTC_CRL_SECF BIT_(0)
+#define CYGHWR_HAL_STM32_RTC_CRL_ALRCF BIT_(1)
+#define CYGHWR_HAL_STM32_RTC_CRL_OWF BIT_(2)
+#define CYGHWR_HAL_STM32_RTC_CRL_RSF BIT_(3)
+#define CYGHWR_HAL_STM32_RTC_CRL_CNF BIT_(4)
+#define CYGHWR_HAL_STM32_RTC_CRL_RTOFF BIT_(5)
//=============================================================================
// External interrupt controller
@@ -526,6 +565,43 @@
#define CYGHWR_HAL_STM32_FLASH_OBR_nRST_STOP BIT_(3)
#define CYGHWR_HAL_STM32_FLASH_OBR_nRST_STDBY BIT_(4)
+//=============================================================================
+// Power control
+
+#define CYGHWR_HAL_STM32_PWR_CR 0x00
+#define CYGHWR_HAL_STM32_PWR_CSR 0x04
+
+// CR fields
+
+#define CYGHWR_HAL_STM32_PWR_CR_LPDS BIT_(0)
+#define CYGHWR_HAL_STM32_PWR_CR_PDDS BIT_(1)
+#define CYGHWR_HAL_STM32_PWR_CR_CWUF BIT_(2)
+#define CYGHWR_HAL_STM32_PWR_CR_CSBF BIT_(3)
+#define CYGHWR_HAL_STM32_PWR_CR_PVDE BIT_(4)
+#define CYGHWR_HAL_STM32_PWR_CR_PLS_XXX VALUE_(5,7)
+#define CYGHWR_HAL_STM32_PWR_CR_DBP BIT_(8)
+
+// CSR fields
+
+#define CYGHWR_HAL_STM32_PWR_CSR_WUF BIT_(0)
+#define CYGHWR_HAL_STM32_PWR_CSR_SBF BIT_(1)
+#define CYGHWR_HAL_STM32_PWR_CSR_PVDO BIT_(2)
+#define CYGHWR_HAL_STM32_PWR_CSR_EWUP BIT_(8)
+
+// Functions and macros to reset the backup domain as well as
+// enable/disable backup domain write protection.
+
+__externC void hal_stm32_bd_unprotect( int disable );
+
+#define CYGHWR_HAL_STM32_BD_RESET() \
+ CYG_MACRO_START \
+ HAL_WRITE_UINT32(CYGHWR_HAL_STM32_RCC+CYGHWR_HAL_STM32_RCC_BDCR, \
+ CYGHWR_HAL_STM32_RCC_BDCR_BDRST); \
+ HAL_WRITE_UINT32(CYGHWR_HAL_STM32_RCC+CYGHWR_HAL_STM32_RCC_BDCR, 0); \
+ CYG_MACRO_END
+
+#define CYGHWR_HAL_STM32_BD_UNPROTECT(__unprotect ) \
+ hal_stm32_bd_unprotect( __unprotect )
//=============================================================================
// FSMC
diff -r c7133bab1df6 packages/hal/cortexm/stm32/var/current/src/stm32_misc.c
--- a/packages/hal/cortexm/stm32/var/current/src/stm32_misc.c Thu Nov 06 11:46:59 2008 +0100
+++ b/packages/hal/cortexm/stm32/var/current/src/stm32_misc.c Thu Nov 06 11:48:27 2008 +0100
@@ -310,6 +310,22 @@
}
//==========================================================================
+// Backup domain
+
+void hal_stm32_bd_unprotect( int unprotect )
+{
+ CYG_ADDRESS pwr = CYGHWR_HAL_STM32_PWR;
+ cyg_uint32 cr;
+
+ HAL_READ_UINT32( pwr+CYGHWR_HAL_STM32_PWR_CR, cr );
+ if( unprotect )
+ cr |= CYGHWR_HAL_STM32_PWR_CR_DBP;
+ else
+ cr &= CYGHWR_HAL_STM32_PWR_CR_DBP;
+ HAL_WRITE_UINT32( pwr+CYGHWR_HAL_STM32_PWR_CR, cr );
+}
+
+//==========================================================================
// UART baud rate
//
// Set the baud rate divider of a UART based on the requested rate and