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SPI lpc2xxx patch


Hi

I never try SPI driver for lpc2xxx before, today I did and found an
annoyance copy & paste typo in spi_lpc2xxx_set_config(). Also, to be
ensure the SPI interrupts are using different, was entered a priority
selector, like that was done for the lpc2xxx serial driver.

Sergei
Index: lpc2xxx/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/spi/arm/lpc2xxx/current/ChangeLog,v
retrieving revision 1.1
diff -U5 -r1.1 ChangeLog
--- lpc2xxx/current/ChangeLog	12 Jul 2008 15:56:10 -0000	1.1
+++ lpc2xxx/current/ChangeLog	27 Jan 2009 09:47:01 -0000
@@ -1,5 +1,13 @@
+2009-01-27  Sergei Gavrikov  <sergei.gavrikov@gmail.com>
+
+	* cdl/spi_lpc2xxx.cdl: Ensure the SPI interrupts are using different
+	priorities: CYGNUM_IO_SPI_ARM_LPC2XXX_SPI{0,1}_INTPRIO entered.
+	* include/spi_lpc2xxx.h: cyg_spi_lpc2xxx_bus_t: spi_prio field added.
+	* src/spi_lpc2xxx.cxx: spi_lpc2xxx_set_config(): fixed copy & paste
+	typo, spi_lpc2xxx_init_bus(): added 'prio' argument to initializer.
+
 2007-07-12  Hans Rosenfeld  <rosenfeld@grumpf.hope-2000.org>
 
 	* lpc2xxx: driver for on-chip SPI units
 
 //===========================================================================
Index: lpc2xxx/current/cdl/spi_lpc2xxx.cdl
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/spi/arm/lpc2xxx/current/cdl/spi_lpc2xxx.cdl,v
retrieving revision 1.1
diff -U5 -r1.1 spi_lpc2xxx.cdl
--- lpc2xxx/current/cdl/spi_lpc2xxx.cdl	12 Jul 2008 15:56:10 -0000	1.1
+++ lpc2xxx/current/cdl/spi_lpc2xxx.cdl	27 Jan 2009 09:47:02 -0000
@@ -61,13 +61,41 @@
         default_value 1
         description   "The LPC2xxx controllers contain two SPI interfaces.
                        Enable this option to get support for SPI interface 0."
     }
 
+    cdl_option CYGNUM_IO_SPI_ARM_LPC2XXX_SPI0_INTPRIO {
+         display "Interrupt priority of the SPI bus 0 ISR"
+         flavor  data
+         legal_values 0 to 15
+         default_value 12
+         requires { is_active(CYGNUM_IO_SPI_ARM_LPC2XXX_SPI1_INTPRIO)
+           implies CYGNUM_IO_SPI_ARM_LPC2XXX_SPI0_INTPRIO !=
+                   CYGNUM_IO_SPI_ARM_LPC2XXX_SPI1_INTPRIO 
+         }
+         description "
+             This option specifies the interrupt priority of the ISR of
+             the SPI bus 0 interrupt in the VIC. Slot 0 has the highest
+             priority and slot 15 the lowest."
+    }
+
     cdl_option CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS1 {
         display       "Enable SPI interface 1"
         flavor        bool
         default_value 1
         description   "The LPC2xxx controllers contain two SPI interfaces.
                        Enable this option to get support for SPI interface 1."
     }
-}
\ No newline at end of file
+
+    cdl_option CYGNUM_IO_SPI_ARM_LPC2XXX_SPI1_INTPRIO {
+         display "Interrupt priority of the SPI bus 1 ISR"
+         flavor  data
+         legal_values 0 to 15
+         default_value 13
+         description "
+             This option specifies the interrupt priority of the ISR of
+             the SPI bus 1 interrupt in the VIC. Slot 0 has the highest
+             priority and slot 15 the lowest."
+    }
+
+}
+
Index: lpc2xxx/current/include/spi_lpc2xxx.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/spi/arm/lpc2xxx/current/include/spi_lpc2xxx.h,v
retrieving revision 1.1
diff -U5 -r1.1 spi_lpc2xxx.h
--- lpc2xxx/current/include/spi_lpc2xxx.h	12 Jul 2008 15:56:10 -0000	1.1
+++ lpc2xxx/current/include/spi_lpc2xxx.h	27 Jan 2009 09:47:02 -0000
@@ -71,10 +71,11 @@
   cyg_spi_bus     spi_bus;
   
   cyg_interrupt   spi_intr;
   cyg_handle_t    spi_hand;
   cyg_vector_t    spi_vect;
+  cyg_priority_t  spi_prio;
   cyg_drv_mutex_t spi_lock;
   cyg_drv_cond_t  spi_wait;
   
   struct spi_dev *spi_dev;
   
Index: lpc2xxx/current/src/spi_lpc2xxx.cxx
===================================================================
RCS file: /cvs/ecos/ecos/packages/devs/spi/arm/lpc2xxx/current/src/spi_lpc2xxx.cxx,v
retrieving revision 1.1
diff -U5 -r1.1 spi_lpc2xxx.cxx
--- lpc2xxx/current/src/spi_lpc2xxx.cxx	12 Jul 2008 15:56:10 -0000	1.1
+++ lpc2xxx/current/src/spi_lpc2xxx.cxx	27 Jan 2009 09:47:02 -0000
@@ -179,11 +179,11 @@
                        cyg_uint32 *len)
 {
   cyg_spi_lpc2xxx_dev_t *dev = (cyg_spi_lpc2xxx_dev_t *) device;
   
   switch(key) {
-    case CYG_IO_GET_CONFIG_SPI_CLOCKRATE:
+    case CYG_IO_SET_CONFIG_SPI_CLOCKRATE:
       if(*len == sizeof(cyg_uint32)) {
         dev->spi_baud = * (cyg_uint32 *) buf;
         spi_lpc2xxx_baud((cyg_spi_lpc2xxx_bus_t *) dev->spi_device.spi_bus, 
                          dev->spi_baud);
       }
@@ -303,11 +303,12 @@
  * Driver & bus initialization
  */
 static void 
 spi_lpc2xxx_init_bus(cyg_spi_lpc2xxx_bus_t *bus, 
                      cyg_addrword_t dev,
-                     cyg_vector_t vec)
+                     cyg_vector_t vec,
+                     cyg_priority_t prio)
 {
   bus->spi_bus.spi_transaction_begin    = spi_lpc2xxx_begin;
   bus->spi_bus.spi_transaction_transfer = spi_lpc2xxx_transfer;
   bus->spi_bus.spi_transaction_tick     = spi_lpc2xxx_tick;
   bus->spi_bus.spi_transaction_end      = spi_lpc2xxx_end;
@@ -318,12 +319,13 @@
   cyg_drv_mutex_init(&bus->spi_lock);
   cyg_drv_cond_init(&bus->spi_wait, &bus->spi_lock);
   
   bus->spi_dev = (struct spi_dev *) dev;
   bus->spi_vect = vec;
+  bus->spi_prio = prio;
   cyg_drv_interrupt_create(
-                           vec, 0, (cyg_addrword_t) bus,
+                           vec, prio, (cyg_addrword_t) bus,
                            &spi_lpc2xxx_isr, &spi_lpc2xxx_dsr,
                            &bus->spi_hand, &bus->spi_intr);
   cyg_drv_interrupt_attach(bus->spi_hand);
 }
 
@@ -342,21 +344,23 @@
     tmp |= 0x5500;
     HAL_WRITE_UINT32(addr, tmp);
     
     spi_lpc2xxx_init_bus(&cyg_spi_lpc2xxx_bus0,
                          CYGARC_HAL_LPC2XXX_REG_SPI0_BASE,
-                         CYGNUM_HAL_INTERRUPT_SPI0);
+                         CYGNUM_HAL_INTERRUPT_SPI0,
+                         CYGNUM_IO_SPI_ARM_LPC2XXX_SPI0_INTPRIO);
 #endif
 #ifdef CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS1
     addr = (CYGARC_HAL_LPC2XXX_REG_PIN_BASE
             + CYGARC_HAL_LPC2XXX_REG_PINSEL1);
     HAL_READ_UINT32(addr, tmp);
     tmp |= 0x2a8;
     HAL_WRITE_UINT32(addr, tmp);
     spi_lpc2xxx_init_bus(&cyg_spi_lpc2xxx_bus1,
                          CYGARC_HAL_LPC2XXX_REG_SPI1_BASE,
-                         CYGNUM_HAL_INTERRUPT_SPI1);
+                         CYGNUM_HAL_INTERRUPT_SPI1,
+                         CYGNUM_IO_SPI_ARM_LPC2XXX_SPI1_INTPRIO);
 #endif
   }
 };
 
 static cyg_spi_lpc2xxx_init_class spi_lpc2xxx_init 

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