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STM32 SPI driver - get rid of 'manual' bus selection.
- From: Chris Holgate <chris at zynaptic dot com>
- To: ecos-patches at sourceware dot org
- Date: Thu, 12 Feb 2009 10:41:35 +0000
- Subject: STM32 SPI driver - get rid of 'manual' bus selection.
The attached patch splits out the data and init functions for each SPI
bus into separate compile units so that it can be left to the linker to
decide which are required. As previously discussed here:
http://ecos.sourceware.org/ml/ecos-patches/2009-02/msg00063.html
Tested using simple loopback test for SPI2 and SPI3. Tested using
M25Pxx test harness for SPI1.
I'll try to have a look at getting rid of the CDL chip select setup if I
get time later.
Chris.
diff -r -N -u5 cvs-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/cdl/spi_stm32.cdl working-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/cdl/spi_stm32.cdl
--- cvs-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/cdl/spi_stm32.cdl 2009-02-10 22:32:03.000000000 +0000
+++ working-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/cdl/spi_stm32.cdl 2009-02-11 18:36:23.000000000 +0000
@@ -56,11 +56,11 @@
parent CYGPKG_IO_SPI
active_if CYGPKG_IO_SPI
requires CYGPKG_HAL_CORTEXM_STM32
hardware
include_dir cyg/io
- compile spi_stm32.c
+ compile spi_stm32.c spi_stm32_bus1.c spi_stm32_bus2.c spi_stm32_bus3.c
cdl_option CYGNUM_DEVS_SPI_CORTEXM_STM32_PIN_TOGGLE_RATE {
display "Pin toggle rate"
description "
Selects the pin toggle rate in MHz to be used for the SPI interfaces. Higher toggle
@@ -71,15 +71,16 @@
legal_values { 2 10 50 }
}
cdl_component CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1 {
display "ST STM32 SPI bus 1"
+ flavor none
description "
- Enable SPI bus 1 on the STM32 device.
+ SPI bus 1 on the STM32 device. If this bus is not used by the
+ application the driver will not be instantiated and the SPI bus I/O
+ pins can be used as normal GPIOs.
"
- flavor bool
- default_value false
cdl_option CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1_CS_GPIOS {
display "SPI chip selects"
description "
This is a comma separated list of GPIOs which are to be used as chip
@@ -116,15 +117,16 @@
}
}
cdl_component CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS2 {
display "ST STM32 SPI bus 2"
+ flavor none
description "
- Enable SPI bus 2 on the STM32 device.
+ SPI bus 2 on the STM32 device. If this bus is not used by the
+ application the driver will not be instantiated and the SPI bus I/O
+ pins can be used as normal GPIOs.
"
- flavor bool
- default_value false
cdl_option CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS2_CS_GPIOS {
display "SPI chip selects"
description "
This is a comma separated list of GPIOs which are to be used as chip
@@ -161,18 +163,19 @@
}
}
cdl_component CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3 {
display "ST STM32 SPI bus 3"
+ flavor none
description "
- Enable SPI bus 3 on the STM32 device. Note that SPI bus 3 shares pins
+ SPI bus 3 on the STM32 device. If this bus is not used by the
+ application the driver will not be instantiated and the SPI bus I/O
+ pins can be used as normal GPIOs. Note that SPI bus 3 shares pins
with the JTAG port which means that debug should ideally be disabled
on startup. However, there is also the option of disabling it during
SPI bus initialisation instead.
"
- flavor bool
- default_value false
cdl_option CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3_DISABLE_DEBUG_PORT {
display "Disable debug port"
description "
When set the debug port will automatically be disabled on
diff -r -N -u5 cvs-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/ChangeLog working-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/ChangeLog
--- cvs-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/ChangeLog 2009-02-10 22:32:03.000000000 +0000
+++ working-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/ChangeLog 2009-02-12 10:26:14.000000000 +0000
@@ -1,5 +1,16 @@
+2009-02-12 Chris Holgate <chris@zynaptic.com>
+
+ * src/spi_stm32.c: Moved per-bus data structures and initialisers out
+ to per-bus compile units. Exported driver API functions.
+ * cdl/spi_stm32.cdl: Added per-bus source files to compile list. The
+ 'bus select' options were removed since unused busses are now stripped
+ out at link time.
+ * src/spi_stm32_bus1.c : New - contains bus 1 data and init function.
+ * src/spi_stm32_bus2.c : New - contains bus 2 data and init function.
+ * src/spi_stm32_bus3.c : New - contains bus 3 data and init function.
+
2009-02-10 Bart Veer <bartv@ecoscentric.com>
* src/spi_stm32.c (cyg_spi_cortexm_stm32_init): mark as
prioritized constructor and rename.
diff -r -N -u5 cvs-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/src/spi_stm32_bus1.c working-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/src/spi_stm32_bus1.c
--- cvs-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/src/spi_stm32_bus1.c 1970-01-01 01:00:00.000000000 +0100
+++ working-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/src/spi_stm32_bus1.c 2009-02-11 18:24:19.000000000 +0000
@@ -0,0 +1,127 @@
+//=============================================================================
+//
+// spi_stm32_bus1.c
+//
+// SPI driver implementation for STM32
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008, 2009 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Chris Holgate
+// Date: 2009-02-11
+// Purpose: STM32 SPI bus 1 initialisation
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/io/spi.h>
+#include <cyg/io/spi_stm32.h>
+
+#include <pkgconf/devs_spi_cortexm_stm32.h>
+
+//-----------------------------------------------------------------------------
+// Pull in the SPI driver API functions.
+
+extern void cyg_spi_stm32_bus_init (cyg_spi_cortexm_stm32_bus_t*);
+extern void cyg_spi_stm32_transaction_begin (cyg_spi_device*);
+extern void cyg_spi_stm32_transaction_transfer (cyg_spi_device*, cyg_bool, cyg_uint32, const cyg_uint8*, cyg_uint8*, cyg_bool);
+extern void cyg_spi_stm32_transaction_tick (cyg_spi_device*, cyg_bool, cyg_uint32);
+extern void cyg_spi_stm32_transaction_end (cyg_spi_device*);
+extern int cyg_spi_stm32_get_config (cyg_spi_device*, cyg_uint32, void*, cyg_uint32*);
+extern int cyg_spi_stm32_set_config (cyg_spi_device*, cyg_uint32, const void*, cyg_uint32*);
+
+//-----------------------------------------------------------------------------
+// Work out the bus clock frequencies.
+
+#define APB2_FREQ ((CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK * CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL) / \
+ (CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV * CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV))
+
+//-----------------------------------------------------------------------------
+// Instantiate the bus 1 setup data structure.
+
+static const cyg_uint8 bus1_cs_gpio_list[] = { CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1_CS_GPIOS };
+static const cyg_uint8 bus1_spi_gpio_list[] = { 0x05, 0x06, 0x07 };
+
+#if (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_BBUF_SIZE > 0)
+static cyg_uint8 bus1_tx_bbuf [CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_BBUF_SIZE]
+ __attribute__((aligned (2), section (".sram"))) = { 0 };
+static cyg_uint8 bus1_rx_bbuf [CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_BBUF_SIZE]
+ __attribute__((aligned (2), section (".sram"))) = { 0 };
+#endif
+
+static const cyg_spi_cortexm_stm32_bus_setup_t bus1_setup = {
+ .apb_freq = APB2_FREQ,
+ .spi_reg_base = CYGHWR_HAL_STM32_SPI1,
+ .dma_reg_base = CYGHWR_HAL_STM32_DMA1,
+ .dma_tx_channel = 3,
+ .dma_rx_channel = 2,
+ .cs_gpio_num = sizeof (bus1_cs_gpio_list),
+ .cs_gpio_list = bus1_cs_gpio_list,
+ .spi_gpio_list = bus1_spi_gpio_list,
+ .dma_tx_intr = CYGNUM_HAL_INTERRUPT_DMA1_CH3,
+ .dma_rx_intr = CYGNUM_HAL_INTERRUPT_DMA1_CH2,
+ .dma_tx_intr_pri = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_TXINTR_PRI,
+ .dma_rx_intr_pri = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_RXINTR_PRI,
+#if (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_BBUF_SIZE > 0)
+ .bbuf_size = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_BBUF_SIZE,
+ .bbuf_tx = bus1_tx_bbuf,
+ .bbuf_rx = bus1_rx_bbuf,
+#else
+ .bbuf_size = 0,
+#endif
+};
+
+cyg_spi_cortexm_stm32_bus_t cyg_spi_stm32_bus1 = {
+ .spi_bus.spi_transaction_begin = cyg_spi_stm32_transaction_begin,
+ .spi_bus.spi_transaction_transfer = cyg_spi_stm32_transaction_transfer,
+ .spi_bus.spi_transaction_tick = cyg_spi_stm32_transaction_tick,
+ .spi_bus.spi_transaction_end = cyg_spi_stm32_transaction_end,
+ .spi_bus.spi_get_config = cyg_spi_stm32_get_config,
+ .spi_bus.spi_set_config = cyg_spi_stm32_set_config,
+ .setup = &bus1_setup,
+ .cs_up = false
+};
+
+//-----------------------------------------------------------------------------
+// Initialisation function for SPI bus 1.
+
+static void CYGBLD_ATTRIB_C_INIT_PRI(CYG_INIT_BUS_SPI)
+stm32_spi_bus1_init (void)
+{
+ cyg_spi_stm32_bus_init (&cyg_spi_stm32_bus1);
+}
+
+//-----------------------------------------------------------------------------
diff -r -N -u5 cvs-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/src/spi_stm32_bus2.c working-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/src/spi_stm32_bus2.c
--- cvs-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/src/spi_stm32_bus2.c 1970-01-01 01:00:00.000000000 +0100
+++ working-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/src/spi_stm32_bus2.c 2009-02-11 18:23:36.000000000 +0000
@@ -0,0 +1,127 @@
+//=============================================================================
+//
+// spi_stm32_bus2.c
+//
+// SPI driver implementation for STM32
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008, 2009 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Chris Holgate
+// Date: 2009-02-11
+// Purpose: STM32 SPI bus 2 initialisation
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/io/spi.h>
+#include <cyg/io/spi_stm32.h>
+
+#include <pkgconf/devs_spi_cortexm_stm32.h>
+
+//-----------------------------------------------------------------------------
+// Pull in the SPI driver API functions.
+
+extern void cyg_spi_stm32_bus_init (cyg_spi_cortexm_stm32_bus_t*);
+extern void cyg_spi_stm32_transaction_begin (cyg_spi_device*);
+extern void cyg_spi_stm32_transaction_transfer (cyg_spi_device*, cyg_bool, cyg_uint32, const cyg_uint8*, cyg_uint8*, cyg_bool);
+extern void cyg_spi_stm32_transaction_tick (cyg_spi_device*, cyg_bool, cyg_uint32);
+extern void cyg_spi_stm32_transaction_end (cyg_spi_device*);
+extern int cyg_spi_stm32_get_config (cyg_spi_device*, cyg_uint32, void*, cyg_uint32*);
+extern int cyg_spi_stm32_set_config (cyg_spi_device*, cyg_uint32, const void*, cyg_uint32*);
+
+//-----------------------------------------------------------------------------
+// Work out the bus clock frequencies.
+
+#define APB1_FREQ ((CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK * CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL) / \
+ (CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV * CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV))
+
+//-----------------------------------------------------------------------------
+// Instantiate the bus 2 setup data structure.
+
+static const cyg_uint8 bus2_cs_gpio_list[] = { CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS2_CS_GPIOS };
+static const cyg_uint8 bus2_spi_gpio_list[] = { 0x1D, 0x1E, 0x1F };
+
+#if (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_BBUF_SIZE > 0)
+static cyg_uint8 bus2_tx_bbuf [CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_BBUF_SIZE]
+ __attribute__((aligned (2), section (".sram"))) = { 0 };
+static cyg_uint8 bus2_rx_bbuf [CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_BBUF_SIZE]
+ __attribute__((aligned (2), section (".sram"))) = { 0 };
+#endif
+
+static const cyg_spi_cortexm_stm32_bus_setup_t bus2_setup = {
+ .apb_freq = APB1_FREQ,
+ .spi_reg_base = CYGHWR_HAL_STM32_SPI2,
+ .dma_reg_base = CYGHWR_HAL_STM32_DMA1,
+ .dma_tx_channel = 5,
+ .dma_rx_channel = 4,
+ .cs_gpio_num = sizeof (bus2_cs_gpio_list),
+ .cs_gpio_list = bus2_cs_gpio_list,
+ .spi_gpio_list = bus2_spi_gpio_list,
+ .dma_tx_intr = CYGNUM_HAL_INTERRUPT_DMA1_CH5,
+ .dma_rx_intr = CYGNUM_HAL_INTERRUPT_DMA1_CH4,
+ .dma_tx_intr_pri = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_TXINTR_PRI,
+ .dma_rx_intr_pri = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_RXINTR_PRI,
+#if (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_BBUF_SIZE > 0)
+ .bbuf_size = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_BBUF_SIZE,
+ .bbuf_tx = bus2_tx_bbuf,
+ .bbuf_rx = bus2_rx_bbuf,
+#else
+ .bbuf_size = 0,
+#endif
+};
+
+cyg_spi_cortexm_stm32_bus_t cyg_spi_stm32_bus2 = {
+ .spi_bus.spi_transaction_begin = cyg_spi_stm32_transaction_begin,
+ .spi_bus.spi_transaction_transfer = cyg_spi_stm32_transaction_transfer,
+ .spi_bus.spi_transaction_tick = cyg_spi_stm32_transaction_tick,
+ .spi_bus.spi_transaction_end = cyg_spi_stm32_transaction_end,
+ .spi_bus.spi_get_config = cyg_spi_stm32_get_config,
+ .spi_bus.spi_set_config = cyg_spi_stm32_set_config,
+ .setup = &bus2_setup,
+ .cs_up = false
+};
+
+//-----------------------------------------------------------------------------
+// Initialisation function for SPI bus 2.
+
+static void CYGBLD_ATTRIB_C_INIT_PRI(CYG_INIT_BUS_SPI)
+stm32_spi_bus2_init (void)
+{
+ cyg_spi_stm32_bus_init (&cyg_spi_stm32_bus2);
+}
+
+//-----------------------------------------------------------------------------
diff -r -N -u5 cvs-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/src/spi_stm32_bus3.c working-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/src/spi_stm32_bus3.c
--- cvs-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/src/spi_stm32_bus3.c 1970-01-01 01:00:00.000000000 +0100
+++ working-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/src/spi_stm32_bus3.c 2009-02-11 18:23:00.000000000 +0000
@@ -0,0 +1,136 @@
+//=============================================================================
+//
+// spi_stm32_bus3.c
+//
+// SPI driver implementation for STM32
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 2008, 2009 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Chris Holgate
+// Date: 2009-02-11
+// Purpose: STM32 SPI bus 3 initialisation
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/io/spi.h>
+#include <cyg/io/spi_stm32.h>
+
+#include <pkgconf/devs_spi_cortexm_stm32.h>
+
+//-----------------------------------------------------------------------------
+// Pull in the SPI driver API functions.
+
+extern void cyg_spi_stm32_bus_init (cyg_spi_cortexm_stm32_bus_t*);
+extern void cyg_spi_stm32_transaction_begin (cyg_spi_device*);
+extern void cyg_spi_stm32_transaction_transfer (cyg_spi_device*, cyg_bool, cyg_uint32, const cyg_uint8*, cyg_uint8*, cyg_bool);
+extern void cyg_spi_stm32_transaction_tick (cyg_spi_device*, cyg_bool, cyg_uint32);
+extern void cyg_spi_stm32_transaction_end (cyg_spi_device*);
+extern int cyg_spi_stm32_get_config (cyg_spi_device*, cyg_uint32, void*, cyg_uint32*);
+extern int cyg_spi_stm32_set_config (cyg_spi_device*, cyg_uint32, const void*, cyg_uint32*);
+
+//-----------------------------------------------------------------------------
+// Work out the bus clock frequencies.
+
+#define APB1_FREQ ((CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK * CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL) / \
+ (CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV * CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV))
+
+//-----------------------------------------------------------------------------
+// Instantiate the bus 3 setup data structure.
+
+static const cyg_uint8 bus3_cs_gpio_list[] = { CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3_CS_GPIOS };
+static const cyg_uint8 bus3_spi_gpio_list[] = { 0x13, 0x14, 0x15 };
+
+#if (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_BBUF_SIZE > 0)
+static cyg_uint8 bus3_tx_bbuf [CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_BBUF_SIZE]
+ __attribute__((aligned (2), section (".sram"))) = { 0 };
+static cyg_uint8 bus3_rx_bbuf [CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_BBUF_SIZE]
+ __attribute__((alugned (2), section (".sram"))) = { 0 };
+#endif
+
+static const cyg_spi_cortexm_stm32_bus_setup_t bus3_setup = {
+ .apb_freq = APB1_FREQ,
+ .spi_reg_base = CYGHWR_HAL_STM32_SPI3,
+ .dma_reg_base = CYGHWR_HAL_STM32_DMA2,
+ .dma_tx_channel = 2,
+ .dma_rx_channel = 1,
+ .cs_gpio_num = sizeof (bus3_cs_gpio_list),
+ .cs_gpio_list = bus3_cs_gpio_list,
+ .spi_gpio_list = bus3_spi_gpio_list,
+ .dma_tx_intr = CYGNUM_HAL_INTERRUPT_DMA2_CH2,
+ .dma_rx_intr = CYGNUM_HAL_INTERRUPT_DMA2_CH1,
+ .dma_tx_intr_pri = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_TXINTR_PRI,
+ .dma_rx_intr_pri = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_RXINTR_PRI,
+#if (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_BBUF_SIZE > 0)
+ .bbuf_size = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_BBUF_SIZE,
+ .bbuf_tx = bus3_tx_bbuf,
+ .bbuf_rx = bus3_rx_bbuf,
+#else
+ .bbuf_size = 0,
+#endif
+};
+
+cyg_spi_cortexm_stm32_bus_t cyg_spi_stm32_bus3 = {
+ .spi_bus.spi_transaction_begin = cyg_spi_stm32_transaction_begin,
+ .spi_bus.spi_transaction_transfer = cyg_spi_stm32_transaction_transfer,
+ .spi_bus.spi_transaction_tick = cyg_spi_stm32_transaction_tick,
+ .spi_bus.spi_transaction_end = cyg_spi_stm32_transaction_end,
+ .spi_bus.spi_get_config = cyg_spi_stm32_get_config,
+ .spi_bus.spi_set_config = cyg_spi_stm32_set_config,
+ .setup = &bus3_setup,
+ .cs_up = false
+};
+
+//-----------------------------------------------------------------------------
+// Initialisation function for SPI bus 3.
+
+static void CYGBLD_ATTRIB_C_INIT_PRI(CYG_INIT_BUS_SPI)
+stm32_spi_bus3_init (void)
+{
+#ifdef CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3_DISABLE_DEBUG_PORT
+ // Disable debug port, freeing up SPI bus 3 pins.
+ cyg_uint32 reg_val;
+ HAL_READ_UINT32 (CYGHWR_HAL_STM32_AFIO + CYGHWR_HAL_STM32_AFIO_MAPR, reg_val);
+ reg_val &= ~((cyg_uint32) CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_MASK);
+ reg_val |= CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_SWDPDIS;
+ HAL_WRITE_UINT32 (CYGHWR_HAL_STM32_AFIO + CYGHWR_HAL_STM32_AFIO_MAPR, reg_val);
+#endif
+
+ cyg_spi_stm32_bus_init (&cyg_spi_stm32_bus3);
+}
+
+//-----------------------------------------------------------------------------
diff -r -N -u5 cvs-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/src/spi_stm32.c working-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/src/spi_stm32.c
--- cvs-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/src/spi_stm32.c 2009-02-10 22:32:03.000000000 +0000
+++ working-11.02.09/ecos/packages//devs/spi/cortexm/stm32/current/src/spi_stm32.c 2009-02-12 10:20:13.000000000 +0000
@@ -72,172 +72,35 @@
(CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV * CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV))
//-----------------------------------------------------------------------------
// API function call forward references.
-static void stm32_transaction_begin (cyg_spi_device*);
-static void stm32_transaction_transfer (cyg_spi_device*, cyg_bool, cyg_uint32, const cyg_uint8*, cyg_uint8*, cyg_bool);
-static void stm32_transaction_tick (cyg_spi_device*, cyg_bool, cyg_uint32);
-static void stm32_transaction_end (cyg_spi_device*);
-static int stm32_get_config (cyg_spi_device*, cyg_uint32, void*, cyg_uint32*);
-static int stm32_set_config (cyg_spi_device*, cyg_uint32, const void*, cyg_uint32*);
+void cyg_spi_stm32_bus_init (cyg_spi_cortexm_stm32_bus_t*);
+void cyg_spi_stm32_transaction_begin (cyg_spi_device*);
+void cyg_spi_stm32_transaction_transfer (cyg_spi_device*, cyg_bool, cyg_uint32, const cyg_uint8*, cyg_uint8*, cyg_bool);
+void cyg_spi_stm32_transaction_tick (cyg_spi_device*, cyg_bool, cyg_uint32);
+void cyg_spi_stm32_transaction_end (cyg_spi_device*);
+int cyg_spi_stm32_get_config (cyg_spi_device*, cyg_uint32, void*, cyg_uint32*);
+int cyg_spi_stm32_set_config (cyg_spi_device*, cyg_uint32, const void*, cyg_uint32*);
//-----------------------------------------------------------------------------
// Null data source and sink must be placed in the on-chip SRAM. This is
// either done explicitly (bounce buffers instantiated) or implicitly (no
// bounce buffers implies that the data area is already on SRAM).
-#if (defined (CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1) && (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_BBUF_SIZE > 0)) || \
- (defined (CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS2) && (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_BBUF_SIZE > 0)) || \
- (defined (CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3) && (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_BBUF_SIZE > 0))
+#if (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_BBUF_SIZE > 0) || \
+ (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_BBUF_SIZE > 0) || \
+ (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_BBUF_SIZE > 0)
static cyg_uint16 dma_tx_null __attribute__((section (".sram"))) = 0xFFFF;
static cyg_uint16 dma_rx_null __attribute__((section (".sram"))) = 0xFFFF;
#else
static cyg_uint16 dma_tx_null = 0xFFFF;
static cyg_uint16 dma_rx_null = 0xFFFF;
#endif
//-----------------------------------------------------------------------------
-// Instantiate the bus state data structures.
-
-#ifdef CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1
-static const cyg_uint8 bus1_cs_gpio_list[] = { CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1_CS_GPIOS };
-static const cyg_uint8 bus1_spi_gpio_list[] = { 0x05, 0x06, 0x07 };
-
-#if (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_BBUF_SIZE > 0)
-static cyg_uint8 bus1_tx_bbuf [CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_BBUF_SIZE]
- __attribute__((aligned (2), section (".sram"))) = { 0 };
-static cyg_uint8 bus1_rx_bbuf [CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_BBUF_SIZE]
- __attribute__((aligned (2), section (".sram"))) = { 0 };
-#endif
-
-static const cyg_spi_cortexm_stm32_bus_setup_t bus1_setup = {
- .apb_freq = APB2_FREQ,
- .spi_reg_base = CYGHWR_HAL_STM32_SPI1,
- .dma_reg_base = CYGHWR_HAL_STM32_DMA1,
- .dma_tx_channel = 3,
- .dma_rx_channel = 2,
- .cs_gpio_num = sizeof (bus1_cs_gpio_list),
- .cs_gpio_list = bus1_cs_gpio_list,
- .spi_gpio_list = bus1_spi_gpio_list,
- .dma_tx_intr = CYGNUM_HAL_INTERRUPT_DMA1_CH3,
- .dma_rx_intr = CYGNUM_HAL_INTERRUPT_DMA1_CH2,
- .dma_tx_intr_pri = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_TXINTR_PRI,
- .dma_rx_intr_pri = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_RXINTR_PRI,
-#if (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_BBUF_SIZE > 0)
- .bbuf_size = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS1_BBUF_SIZE,
- .bbuf_tx = bus1_tx_bbuf,
- .bbuf_rx = bus1_rx_bbuf,
-#else
- .bbuf_size = 0,
-#endif
-};
-
-cyg_spi_cortexm_stm32_bus_t cyg_spi_stm32_bus1 = {
- .spi_bus.spi_transaction_begin = stm32_transaction_begin,
- .spi_bus.spi_transaction_transfer = stm32_transaction_transfer,
- .spi_bus.spi_transaction_tick = stm32_transaction_tick,
- .spi_bus.spi_transaction_end = stm32_transaction_end,
- .spi_bus.spi_get_config = stm32_get_config,
- .spi_bus.spi_set_config = stm32_set_config,
- .setup = &bus1_setup,
- .cs_up = false
-};
-#endif
-
-#ifdef CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS2
-static const cyg_uint8 bus2_cs_gpio_list[] = { CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS2_CS_GPIOS };
-static const cyg_uint8 bus2_spi_gpio_list[] = { 0x1D, 0x1E, 0x1F };
-
-#if (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_BBUF_SIZE > 0)
-static cyg_uint8 bus2_tx_bbuf [CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_BBUF_SIZE]
- __attribute__((aligned (2), section (".sram"))) = { 0 };
-static cyg_uint8 bus2_rx_bbuf [CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_BBUF_SIZE]
- __attribute__((aligned (2), section (".sram"))) = { 0 };
-#endif
-
-static const cyg_spi_cortexm_stm32_bus_setup_t bus2_setup = {
- .apb_freq = APB1_FREQ,
- .spi_reg_base = CYGHWR_HAL_STM32_SPI2,
- .dma_reg_base = CYGHWR_HAL_STM32_DMA1,
- .dma_tx_channel = 5,
- .dma_rx_channel = 4,
- .cs_gpio_num = sizeof (bus2_cs_gpio_list),
- .cs_gpio_list = bus2_cs_gpio_list,
- .spi_gpio_list = bus2_spi_gpio_list,
- .dma_tx_intr = CYGNUM_HAL_INTERRUPT_DMA1_CH5,
- .dma_rx_intr = CYGNUM_HAL_INTERRUPT_DMA1_CH4,
- .dma_tx_intr_pri = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_TXINTR_PRI,
- .dma_rx_intr_pri = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_RXINTR_PRI,
-#if (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_BBUF_SIZE > 0)
- .bbuf_size = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS2_BBUF_SIZE,
- .bbuf_tx = bus2_tx_bbuf,
- .bbuf_rx = bus2_rx_bbuf,
-#else
- .bbuf_size = 0,
-#endif
-};
-
-cyg_spi_cortexm_stm32_bus_t cyg_spi_stm32_bus2 = {
- .spi_bus.spi_transaction_begin = stm32_transaction_begin,
- .spi_bus.spi_transaction_transfer = stm32_transaction_transfer,
- .spi_bus.spi_transaction_tick = stm32_transaction_tick,
- .spi_bus.spi_transaction_end = stm32_transaction_end,
- .spi_bus.spi_get_config = stm32_get_config,
- .spi_bus.spi_set_config = stm32_set_config,
- .setup = &bus2_setup,
- .cs_up = false
-};
-#endif
-
-#ifdef CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3
-static const cyg_uint8 bus3_cs_gpio_list[] = { CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3_CS_GPIOS };
-static const cyg_uint8 bus3_spi_gpio_list[] = { 0x13, 0x14, 0x15 };
-
-#if (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_BBUF_SIZE > 0)
-static cyg_uint8 bus3_tx_bbuf [CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_BBUF_SIZE]
- __attribute__((aligned (2), section (".sram"))) = { 0 };
-static cyg_uint8 bus3_rx_bbuf [CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_BBUF_SIZE]
- __attribute__((alugned (2), section (".sram"))) = { 0 };
-#endif
-
-static const cyg_spi_cortexm_stm32_bus_setup_t bus3_setup = {
- .apb_freq = APB1_FREQ,
- .spi_reg_base = CYGHWR_HAL_STM32_SPI3,
- .dma_reg_base = CYGHWR_HAL_STM32_DMA2,
- .dma_tx_channel = 2,
- .dma_rx_channel = 1,
- .cs_gpio_num = sizeof (bus3_cs_gpio_list),
- .cs_gpio_list = bus3_cs_gpio_list,
- .spi_gpio_list = bus3_spi_gpio_list,
- .dma_tx_intr = CYGNUM_HAL_INTERRUPT_DMA2_CH2,
- .dma_rx_intr = CYGNUM_HAL_INTERRUPT_DMA2_CH1,
- .dma_tx_intr_pri = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_TXINTR_PRI,
- .dma_rx_intr_pri = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_RXINTR_PRI,
-#if (CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_BBUF_SIZE > 0)
- .bbuf_size = CYGNUM_DEVS_SPI_CORTEXM_STM32_BUS3_BBUF_SIZE,
- .bbuf_tx = bus3_tx_bbuf,
- .bbuf_rx = bus3_rx_bbuf,
-#else
- .bbuf_size = 0,
-#endif
-};
-
-cyg_spi_cortexm_stm32_bus_t cyg_spi_stm32_bus3 = {
- .spi_bus.spi_transaction_begin = stm32_transaction_begin,
- .spi_bus.spi_transaction_transfer = stm32_transaction_transfer,
- .spi_bus.spi_transaction_tick = stm32_transaction_tick,
- .spi_bus.spi_transaction_end = stm32_transaction_end,
- .spi_bus.spi_get_config = stm32_get_config,
- .spi_bus.spi_set_config = stm32_set_config,
- .setup = &bus3_setup,
- .cs_up = false
-};
-#endif
-
-//-----------------------------------------------------------------------------
// Useful GPIO macros for 'dynamic' pin setup.
static const cyg_uint32 stm32_gpio_port_offsets[] = {
CYGHWR_HAL_STM32_GPIOA - CYGHWR_HAL_STM32_GPIOA,
CYGHWR_HAL_STM32_GPIOB - CYGHWR_HAL_STM32_GPIOA,
@@ -380,11 +243,11 @@
}
//-----------------------------------------------------------------------------
// Set up a new SPI bus on initialisation.
-static void stm32_spi_bus_setup
+void cyg_spi_stm32_bus_init
(cyg_spi_cortexm_stm32_bus_t* stm32_bus)
{
int i;
cyg_haladdress reg_addr;
cyg_uint32 pin, pinspec, reg_data;
@@ -607,42 +470,13 @@
stm32_bus->cs_up = false;
}
}
//-----------------------------------------------------------------------------
-// Initialise SPI interfaces on startup.
-
-static void CYGBLD_ATTRIB_C_INIT_PRI(CYG_INIT_BUS_SPI)
-stm32_spi_init(void)
-{
-#if defined(CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3) && \
- defined(CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3_DISABLE_DEBUG_PORT)
- // Disable debug port, freeing up SPI bus 3 pins.
- cyg_uint32 reg_val;
- HAL_READ_UINT32 (CYGHWR_HAL_STM32_AFIO + CYGHWR_HAL_STM32_AFIO_MAPR, reg_val);
- reg_val &= ~((cyg_uint32) CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_MASK);
- reg_val |= CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_SWDPDIS;
- HAL_WRITE_UINT32 (CYGHWR_HAL_STM32_AFIO + CYGHWR_HAL_STM32_AFIO_MAPR, reg_val);
-#endif
-
-#ifdef CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1
- stm32_spi_bus_setup (&cyg_spi_stm32_bus1);
-#endif
-
-#ifdef CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS2
- stm32_spi_bus_setup (&cyg_spi_stm32_bus2);
-#endif
-
-#ifdef CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3
- stm32_spi_bus_setup (&cyg_spi_stm32_bus3);
-#endif
-}
-
-//-----------------------------------------------------------------------------
// Start a SPI transaction.
-static void stm32_transaction_begin
+void cyg_spi_stm32_transaction_begin
(cyg_spi_device* device)
{
cyg_spi_cortexm_stm32_bus_t* stm32_bus = (cyg_spi_cortexm_stm32_bus_t*) device->spi_bus;
cyg_spi_cortexm_stm32_device_t* stm32_device = (cyg_spi_cortexm_stm32_device_t*) device;
@@ -680,11 +514,11 @@
}
//-----------------------------------------------------------------------------
// Run a transaction transfer.
-static void stm32_transaction_transfer
+void cyg_spi_stm32_transaction_transfer
(cyg_spi_device* device, cyg_bool polled, cyg_uint32 count,
const cyg_uint8* tx_data, cyg_uint8* rx_data, cyg_bool drop_cs)
{
cyg_spi_cortexm_stm32_bus_t* stm32_bus = (cyg_spi_cortexm_stm32_bus_t*) device->spi_bus;
cyg_spi_cortexm_stm32_device_t* stm32_device = (cyg_spi_cortexm_stm32_device_t*) device;
@@ -731,11 +565,11 @@
//-----------------------------------------------------------------------------
// Carry out a bus tick operation - this just pushes the required number of
// zeros onto the bus, leaving the chip select in its current state.
-static void stm32_transaction_tick
+void cyg_spi_stm32_transaction_tick
(cyg_spi_device* device, cyg_bool polled, cyg_uint32 count)
{
cyg_spi_cortexm_stm32_device_t* stm32_device = (cyg_spi_cortexm_stm32_device_t*) device;
// Check for unsupported transactions.
@@ -752,11 +586,11 @@
}
//-----------------------------------------------------------------------------
// Terminate a SPI transaction, disabling the SPI controller.
-static void stm32_transaction_end
+void cyg_spi_stm32_transaction_end
(cyg_spi_device* device)
{
cyg_spi_cortexm_stm32_bus_t* stm32_bus = (cyg_spi_cortexm_stm32_bus_t*) device->spi_bus;
cyg_spi_cortexm_stm32_device_t* stm32_device = (cyg_spi_cortexm_stm32_device_t*) device;
@@ -775,17 +609,17 @@
}
//-----------------------------------------------------------------------------
// Note that no dynamic configuration options are currently defined.
-static int stm32_get_config
+int cyg_spi_stm32_get_config
(cyg_spi_device* dev, cyg_uint32 key, void* buf, cyg_uint32* len)
{
return -1;
}
-static int stm32_set_config
+int cyg_spi_stm32_set_config
(cyg_spi_device* dev, cyg_uint32 key, const void* buf, cyg_uint32* len)
{
return -1;
}