[Bug 1001117] Cortex-M architecture fixes.

[bugzilla-daemon at bugs dot ecos dot sourceware dot org]

Please do not reply to this email. Use the web interface provided at:
http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001117

Christophe Coutand <ecos@hotmail.co.uk> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |ecos@hotmail.co.uk

--- Comment #1 from Christophe Coutand <ecos@hotmail.co.uk> 2011-01-16 10:21:01 GMT ---
Hi Ilija,

I made a patch for the system tick clock source some time ago: Bug 1001090 .

Your patch seems to change the default behavior of the cortex M HAL:

#1 CSR is initialised with CYGARC_REG_SYSTICK_CSR_TICKINT so you are enabling
the interrupt.

#2 Definition of CYGARC_REG_SYSTICK_CSR_CLK_EXT and
CYGARC_REG_SYSTICK_CSR_CLK_INT was originally correct, your new definition is
more difficult to understand. When CYGARC_REG_SYSTICK_CSR_CLK_SRC is not
defined in CDLs, the clock source equal CYGARC_REG_SYSTICK_CSR_CLK_INT which
actually makes the processor use external clock while by reading the code one
might think that the processor should use internal clock.

+#if !defined CYGARC_REG_SYSTICK_CSR_CLK_SRC
+#define CYGARC_REG_SYSTICK_CSR_CLK_SRC CYGARC_REG_SYSTICK_CSR_CLK_INT
+#endif

Christophe

-- 
Configure bugmail: http://bugs.ecos.sourceware.org/userprefs.cgi?tab=email
------- You are receiving this mail because: -------
You are on the CC list for the bug.