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src/sim d10v/ChangeLog d10v/interp.c testsuite ...


CVSROOT:	/cvs/src
Module name:	src
Changes by:	cagney@sourceware.cygnus.com	00/04/18 00:55:35

Modified files:
	sim/d10v       : ChangeLog interp.c 
	sim/testsuite/d10v-elf: ChangeLog Makefile.in 
Added files:
	sim/testsuite/d10v-elf: t-rie-xx.s 

Log message:
	Add support for SIGILL (reserved-instruction-exception).

Patches:
http://sourceware.cygnus.com/cgi-bin/cvsweb.cgi/src/sim/d10v/ChangeLog.diff?cvsroot=src&r1=1.3&r2=1.4
http://sourceware.cygnus.com/cgi-bin/cvsweb.cgi/src/sim/d10v/interp.c.diff?cvsroot=src&r1=1.3&r2=1.4
http://sourceware.cygnus.com/cgi-bin/cvsweb.cgi/src/sim/testsuite/d10v-elf/t-rie-xx.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.cygnus.com/cgi-bin/cvsweb.cgi/src/sim/testsuite/d10v-elf/ChangeLog.diff?cvsroot=src&r1=1.2&r2=1.3
http://sourceware.cygnus.com/cgi-bin/cvsweb.cgi/src/sim/testsuite/d10v-elf/Makefile.in.diff?cvsroot=src&r1=1.2&r2=1.3


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