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src/sim/m68hc11 ChangeLog interrupts.c interru ...
- From: ciceron at sources dot redhat dot com
- To: gdb-cvs at sources dot redhat dot com
- Date: 7 Mar 2002 19:02:18 -0000
- Subject: src/sim/m68hc11 ChangeLog interrupts.c interru ...
CVSROOT: /cvs/src
Module name: src
Branch: gdb_5_2-branch
Changes by: ciceron@sources.redhat.com 2002-03-07 11:02:18
Modified files:
sim/m68hc11 : ChangeLog interrupts.c interrupts.h
m68hc11_sim.c
Log message:
* interrupts.c (interrupts_reset): New function, setup interrupt
vector address according to cpu mode.
(interrupts_initialize): Move reset portion to the above.
(interrupt_names): New table to give a name to interrupts.
(idefs): Handle pulse accumulator interrupts.
(interrupts_info): Print the interrupt history.
(interrupt_option_handler): New function.
(interrupt_options): New table of options.
(interrupts_update_pending): Keep track of when interrupts are
raised and implement breakpoint-on-raise-interrupt.
(interrupts_process): Keep track of when interrupts are taken
and implement breakpoint-on-interrupt.
* interrupts.h (struct interrupt_history): Define.
(struct interrupt): Keep track of the interrupt history.
(interrupts_reset): Declare.
(interrupts_initialize): Update prototype.
* m68hc11_sim.c (cpu_reset): Reset interrupts.
(cpu_initialize): Cleanup.
Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m68hc11/ChangeLog.diff?cvsroot=src&only_with_tag=gdb_5_2-branch&r1=1.17&r2=1.17.8.1
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m68hc11/interrupts.c.diff?cvsroot=src&only_with_tag=gdb_5_2-branch&r1=1.4&r2=1.4.8.1
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m68hc11/interrupts.h.diff?cvsroot=src&only_with_tag=gdb_5_2-branch&r1=1.2&r2=1.2.8.1
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/m68hc11/m68hc11_sim.c.diff?cvsroot=src&only_with_tag=gdb_5_2-branch&r1=1.3&r2=1.3.8.1