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src/sim/h8300 ChangeLog compile.c
- From: msnyder at sources dot redhat dot com
- To: gdb-cvs at sources dot redhat dot com
- Date: 19 Jun 2003 02:14:14 -0000
- Subject: src/sim/h8300 ChangeLog compile.c
CVSROOT: /cvs/src
Module name: src
Changes by: msnyder@sourceware.org 2003-06-19 02:14:14
Modified files:
sim/h8300 : ChangeLog compile.c
Log message:
2003-06-18 Michael Snyder <msnyder@redhat.com>
* compile.c: Replace "Hitachi" with "Renesas".
(decode): Distinguish AV_H8S from AV_H8H.
(sim_resume): H8SX can use any register for TAS.
(decode): Add support for VECIND.
(sim_resume): Implement rte/l and rts/l.
(GETSR): New macro (actually old macro reincarnated).
(decode): Add handling for IMM2.
(sim_resume): Drop extra block around jmp, jsr, rts.
Add handling for trapa and rte.
For divxu.b, change 0xffff mask to 0xff.
(set_h8300h): Add bfd_mach_h8300sxn machine.
Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/h8300/ChangeLog.diff?cvsroot=src&r1=1.32&r2=1.33
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/sim/h8300/compile.c.diff?cvsroot=src&r1=1.30&r2=1.31