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src/sim/m32c ChangeLog mem.c r8c.opc reg.c sys ...
- From: dj at sourceware dot org
- To: gdb-cvs at sources dot redhat dot com
- Date: 14 Mar 2006 03:34:28 -0000
- Subject: src/sim/m32c ChangeLog mem.c r8c.opc reg.c sys ...
CVSROOT: /cvs/src
Module name: src
Changes by: dj@sourceware.org 2006-03-14 03:34:28
Modified files:
sim/m32c : ChangeLog mem.c r8c.opc reg.c syscalls.c
Added files:
sim/m32c : syscall.h
Log message:
* mem.c (mem_put_byte): Hook simulated UART to stdout.
(mem_put_hi): Hook in simulated trace port.
(mem_get_byte): Hook in simulated uart control port.
* opc2c: Be more picky about matching special comments.
* r8c.opc (shift_op): Limit shift counts to -16..16.
(BMcnd): Map conditional codes.
* reg.c (condition_true): Mask condition code to 4 bits.
* syscalls.c: Include local syscall.h.
* syscall.h: New, copied from libgloss.
Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/syscall.h.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/ChangeLog.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/mem.c.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/r8c.opc.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/reg.c.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/m32c/syscalls.c.diff?cvsroot=src&r1=1.1&r2=1.2