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src/sim ChangeLog configure configure.tgt test ...
- From: vapier at sourceware dot org
- To: gdb-cvs at sourceware dot org
- Date: 4 Jun 2011 17:44:22 -0000
- Subject: src/sim ChangeLog configure configure.tgt test ...
CVSROOT: /cvs/src
Module name: src
Changes by: vapier@sourceware.org 2011-06-04 17:44:22
Modified files:
sim : ChangeLog configure configure.tgt
Added files:
sim/testsuite/sim/bfin: 10272_small.s 10436.s 10622.s 10742.s
10799.s 11080.s 7641.s ChangeLog
PN_generator.s a0.s a0shift.S a1.s a10.s
a11.S a12.s a2.s a20.S a21.s a22.s a23.s
a24.s a25.s a26.s a3.s a30.s a4.s a5.s
a6.s a7.s a8.s a9.s abs-2.S abs-3.S
abs-4.S abs.S abs_acc.s acc-rot.s
acp5_19.s acp5_4.s add_imm7.s
add_shift.S add_sub_acc.s addsub_flags.S
algnbug1.s algnbug2.s allinsn.exp argc.c
ashift.s ashift_flags.s b0.S b1.s b2.S
brcc.s brevadd.s byteop16m.s byteop16p.s
byteop1p.s byteop2p.s byteop3p.s
byteunpack.s c_alu2op_arith_r_sft.s
c_alu2op_conv_b.s c_alu2op_conv_h.s
c_alu2op_conv_mix.s c_alu2op_conv_neg.s
c_alu2op_conv_toggle.s
c_alu2op_conv_xb.s c_alu2op_conv_xh.s
c_alu2op_divq.s c_alu2op_divs.s
c_alu2op_log_l_sft.s
c_alu2op_log_r_sft.s c_alu2op_shadd_1.s
c_alu2op_shadd_2.s c_br_preg_killed_ac.s
c_br_preg_killed_ex1.s
c_br_preg_stall_ac.s
c_br_preg_stall_ex1.s c_brcc_bp1.s
c_brcc_bp2.s c_brcc_bp3.s c_brcc_bp4.s
c_brcc_brf_bp.s c_brcc_brf_brt_bp.s
c_brcc_brf_brt_nbp.s c_brcc_brf_fbkwd.s
c_brcc_brf_nbp.s c_brcc_brt_bp.s
c_brcc_brt_nbp.s c_brcc_kills_dhits.s
c_brcc_kills_dmiss.s
c_cactrl_iflush_pr.s
c_cactrl_iflush_pr_pp.s c_calla_ljump.s
c_calla_subr.s c_cc2dreg.s
c_cc2stat_cc_ac.S c_cc2stat_cc_an.s
c_cc2stat_cc_aq.s c_cc2stat_cc_av0.S
c_cc2stat_cc_av1.S c_cc2stat_cc_az.s
c_cc_flag_ccmv_depend.S
c_cc_flagdreg_mvbrsft.s
c_cc_flagdreg_mvbrsft_s1.s
c_cc_flagdreg_mvbrsft_sn.s
c_cc_regmvlogi_mvbrsft.s
c_cc_regmvlogi_mvbrsft_s1.s
c_cc_regmvlogi_mvbrsft_sn.S
c_ccflag_a0a1.S c_ccflag_dr_dr.s
c_ccflag_dr_dr_uu.s c_ccflag_dr_imm3.s
c_ccflag_dr_imm3_uu.s c_ccflag_pr_imm3.s
c_ccflag_pr_imm3_uu.s c_ccflag_pr_pr.s
c_ccflag_pr_pr_uu.s c_ccmv_cc_dr_dr.s
c_ccmv_cc_dr_pr.s c_ccmv_cc_pr_pr.s
c_ccmv_ncc_dr_dr.s c_ccmv_ncc_dr_pr.s
c_ccmv_ncc_pr_pr.s c_comp3op_dr_and_dr.s
c_comp3op_dr_minus_dr.s
c_comp3op_dr_mix.s c_comp3op_dr_or_dr.s
c_comp3op_dr_plus_dr.s
c_comp3op_dr_xor_dr.s
c_comp3op_pr_plus_pr_sh1.s
c_comp3op_pr_plus_pr_sh2.s
c_compi2opd_dr_add_i7_n.s
c_compi2opd_dr_add_i7_p.s
c_compi2opd_dr_eq_i7_n.s
c_compi2opd_dr_eq_i7_p.s
c_compi2opd_flags.S
c_compi2opd_flags_2.S
c_compi2opp_pr_add_i7_n.s
c_compi2opp_pr_add_i7_p.s
c_compi2opp_pr_eq_i7_n.s
c_compi2opp_pr_eq_i7_p.s
c_dagmodik_lnz_imgebl.s
c_dagmodik_lnz_imltbl.s
c_dagmodik_lz_inc_dec.s
c_dagmodim_lnz_imgebl.s
c_dagmodim_lnz_imltbl.s
c_dagmodim_lz_inc_dec.s
c_dsp32alu_a0_pm_a1.s c_dsp32alu_a0a1s.s
c_dsp32alu_a_abs_a.s
c_dsp32alu_a_neg_a.s
c_dsp32alu_aa_absabs.s
c_dsp32alu_aa_negneg.s c_dsp32alu_abs.s
c_dsp32alu_absabs.s c_dsp32alu_alhwx.s
c_dsp32alu_awx.s c_dsp32alu_byteop1ew.s
c_dsp32alu_byteop2.s
c_dsp32alu_byteop3.s
c_dsp32alu_bytepack.s
c_dsp32alu_byteunpack.s
c_dsp32alu_disalnexcpt.s
c_dsp32alu_max.s c_dsp32alu_maxmax.s
c_dsp32alu_min.s c_dsp32alu_minmin.s
c_dsp32alu_mix.s c_dsp32alu_r_lh_a0pa1.s
c_dsp32alu_r_negneg.s c_dsp32alu_rh_m.s
c_dsp32alu_rh_p.s
c_dsp32alu_rh_rnd12_m.s
c_dsp32alu_rh_rnd12_p.s
c_dsp32alu_rh_rnd20_m.s
c_dsp32alu_rh_rnd20_p.s
c_dsp32alu_rl_m.s c_dsp32alu_rl_p.s
c_dsp32alu_rl_rnd12_m.s
c_dsp32alu_rl_rnd12_p.s
c_dsp32alu_rl_rnd20_m.s
c_dsp32alu_rl_rnd20_p.s
c_dsp32alu_rlh_rnd.s c_dsp32alu_rm.s
c_dsp32alu_rmm.s c_dsp32alu_rmp.s
c_dsp32alu_rp.s c_dsp32alu_rpm.s
c_dsp32alu_rpp.s
c_dsp32alu_rr_lph_a1a0.s
c_dsp32alu_rrpm.s c_dsp32alu_rrpm_aa.s
c_dsp32alu_rrpmmp.s
c_dsp32alu_rrpmmp_sft.s
c_dsp32alu_rrpmmp_sft_x.s
c_dsp32alu_rrppmm.s
c_dsp32alu_rrppmm_sft.s
c_dsp32alu_rrppmm_sft_x.s
c_dsp32alu_saa.s c_dsp32alu_sat_aa.S
c_dsp32alu_search.s c_dsp32alu_sgn.s
c_dsp32mac_a1a0.s
c_dsp32mac_a1a0_iuw32.s
c_dsp32mac_a1a0_m.s c_dsp32mac_dr_a0.s
c_dsp32mac_dr_a0_i.s
c_dsp32mac_dr_a0_ih.s
c_dsp32mac_dr_a0_is.s
c_dsp32mac_dr_a0_iu.s
c_dsp32mac_dr_a0_m.s
c_dsp32mac_dr_a0_s.s
c_dsp32mac_dr_a0_t.s
c_dsp32mac_dr_a0_tu.s
c_dsp32mac_dr_a0_u.s c_dsp32mac_dr_a1.s
c_dsp32mac_dr_a1_i.s
c_dsp32mac_dr_a1_ih.s
c_dsp32mac_dr_a1_is.s
c_dsp32mac_dr_a1_iu.s
c_dsp32mac_dr_a1_m.s
c_dsp32mac_dr_a1_s.s
c_dsp32mac_dr_a1_t.s
c_dsp32mac_dr_a1_tu.s
c_dsp32mac_dr_a1_u.s
c_dsp32mac_dr_a1a0.s
c_dsp32mac_dr_a1a0_iutsh.s
c_dsp32mac_dr_a1a0_m.s c_dsp32mac_mix.s
c_dsp32mac_pair_a0.s
c_dsp32mac_pair_a0_i.s
c_dsp32mac_pair_a0_is.s
c_dsp32mac_pair_a0_m.s
c_dsp32mac_pair_a0_s.s
c_dsp32mac_pair_a0_u.s
c_dsp32mac_pair_a1.s
c_dsp32mac_pair_a1_i.s
c_dsp32mac_pair_a1_is.s
c_dsp32mac_pair_a1_m.s
c_dsp32mac_pair_a1_s.s
c_dsp32mac_pair_a1_u.s
c_dsp32mac_pair_a1a0.s
c_dsp32mac_pair_a1a0_i.s
c_dsp32mac_pair_a1a0_is.s
c_dsp32mac_pair_a1a0_m.s
c_dsp32mac_pair_a1a0_s.s
c_dsp32mac_pair_a1a0_u.s
c_dsp32mac_pair_mix.s c_dsp32mult_dr.s
c_dsp32mult_dr_i.s c_dsp32mult_dr_ih.s
c_dsp32mult_dr_is.s c_dsp32mult_dr_iu.s
c_dsp32mult_dr_m.s c_dsp32mult_dr_m_i.s
c_dsp32mult_dr_m_iutsh.s
c_dsp32mult_dr_m_s.s
c_dsp32mult_dr_m_t.s
c_dsp32mult_dr_m_u.s
c_dsp32mult_dr_mix.s c_dsp32mult_dr_s.s
c_dsp32mult_dr_t.s c_dsp32mult_dr_tu.s
c_dsp32mult_dr_u.s c_dsp32mult_pair.s
c_dsp32mult_pair_i.s
c_dsp32mult_pair_is.s
c_dsp32mult_pair_m.s
c_dsp32mult_pair_m_i.s
c_dsp32mult_pair_m_is.s
c_dsp32mult_pair_m_s.s
c_dsp32mult_pair_m_u.s
c_dsp32mult_pair_s.s
c_dsp32mult_pair_u.s
c_dsp32shift_a0alr.s c_dsp32shift_af.s
c_dsp32shift_af_s.s
c_dsp32shift_ahalf_ln.s
c_dsp32shift_ahalf_ln_s.s
c_dsp32shift_ahalf_lp.s
c_dsp32shift_ahalf_lp_s.s
c_dsp32shift_ahalf_rn.s
c_dsp32shift_ahalf_rn_s.s
c_dsp32shift_ahalf_rp.s
c_dsp32shift_ahalf_rp_s.s
c_dsp32shift_ahh.s c_dsp32shift_ahh_s.s
c_dsp32shift_align16.s
c_dsp32shift_align24.s
c_dsp32shift_align8.s
c_dsp32shift_amix.s
c_dsp32shift_bitmux.s
c_dsp32shift_bxor.s
c_dsp32shift_expadj_h.s
c_dsp32shift_expadj_l.s
c_dsp32shift_expadj_r.s
c_dsp32shift_expexp_r.s
c_dsp32shift_fdepx.s
c_dsp32shift_fextx.s c_dsp32shift_lf.s
c_dsp32shift_lhalf_ln.s
c_dsp32shift_lhalf_lp.s
c_dsp32shift_lhalf_rn.s
c_dsp32shift_lhalf_rp.s
c_dsp32shift_lhh.s c_dsp32shift_lmix.s
c_dsp32shift_ones.s c_dsp32shift_pack.s
c_dsp32shift_rot.s
c_dsp32shift_rot_mix.s
c_dsp32shift_signbits_r.s
c_dsp32shift_signbits_rh.s
c_dsp32shift_signbits_rl.s
c_dsp32shift_vmax.s
c_dsp32shift_vmaxvmax.s
c_dsp32shiftim_a0alr.s
c_dsp32shiftim_af.s
c_dsp32shiftim_af_s.s
c_dsp32shiftim_ahalf_ln.s
c_dsp32shiftim_ahalf_ln_s.s
c_dsp32shiftim_ahalf_lp.s
c_dsp32shiftim_ahalf_lp_s.s
c_dsp32shiftim_ahalf_rn.s
c_dsp32shiftim_ahalf_rn_s.s
c_dsp32shiftim_ahalf_rp.s
c_dsp32shiftim_ahalf_rp_s.s
c_dsp32shiftim_ahh.s
c_dsp32shiftim_ahh_s.s
c_dsp32shiftim_amix.s
c_dsp32shiftim_lf.s
c_dsp32shiftim_lhalf_ln.s
c_dsp32shiftim_lhalf_lp.s
c_dsp32shiftim_lhalf_rn.s
c_dsp32shiftim_lhalf_rp.s
c_dsp32shiftim_lhh.s
c_dsp32shiftim_lmix.s
c_dsp32shiftim_rot.s c_dspldst_ld_dr_i.s
c_dspldst_ld_dr_ipp.s
c_dspldst_ld_dr_ippm.s
c_dspldst_ld_drhi_i.s
c_dspldst_ld_drhi_ipp.s
c_dspldst_ld_drlo_i.s
c_dspldst_ld_drlo_ipp.s
c_dspldst_st_dr_i.s
c_dspldst_st_dr_ipp.s
c_dspldst_st_dr_ippm.s
c_dspldst_st_drhi_i.s
c_dspldst_st_drhi_ipp.s
c_dspldst_st_drlo_i.s
c_dspldst_st_drlo_ipp.s
c_except_illopcode.S
c_except_sys_sstep.S
c_except_user_mode.S c_interr_disable.S
c_interr_disable_enable.S
c_interr_excpt.S
c_interr_loopsetup_stld.S
c_interr_nested.S c_interr_nmi.S
c_interr_pending.S c_interr_pending_2.S
c_interr_timer.S c_interr_timer_reload.S
c_interr_timer_tcount.S
c_interr_timer_tscale.S
c_ldimmhalf_dreg.s c_ldimmhalf_drhi.s
c_ldimmhalf_drlo.s c_ldimmhalf_h_dr.s
c_ldimmhalf_h_ibml.s c_ldimmhalf_h_pr.s
c_ldimmhalf_l_dr.s c_ldimmhalf_l_ibml.s
c_ldimmhalf_l_pr.s c_ldimmhalf_lz_dr.s
c_ldimmhalf_lz_ibml.s
c_ldimmhalf_lz_pr.s
c_ldimmhalf_lzhi_dr.s
c_ldimmhalf_lzhi_ibml.s
c_ldimmhalf_lzhi_pr.s
c_ldimmhalf_pibml.s c_ldst_ld_d_p.s
c_ldst_ld_d_p_b.s c_ldst_ld_d_p_h.s
c_ldst_ld_d_p_mm.s c_ldst_ld_d_p_mm_b.s
c_ldst_ld_d_p_mm_h.s
c_ldst_ld_d_p_mm_xb.s
c_ldst_ld_d_p_mm_xh.s c_ldst_ld_d_p_pp.s
c_ldst_ld_d_p_pp_b.s
c_ldst_ld_d_p_pp_h.s
c_ldst_ld_d_p_pp_xb.s
c_ldst_ld_d_p_pp_xh.s
c_ldst_ld_d_p_ppmm_hbx.s
c_ldst_ld_d_p_xb.s c_ldst_ld_d_p_xh.s
c_ldst_ld_p_p.s c_ldst_ld_p_p_mm.s
c_ldst_ld_p_p_pp.s c_ldst_st_p_d.s
c_ldst_st_p_d_b.s c_ldst_st_p_d_h.s
c_ldst_st_p_d_mm.s c_ldst_st_p_d_mm_b.s
c_ldst_st_p_d_mm_h.s c_ldst_st_p_d_pp.s
c_ldst_st_p_d_pp_b.s
c_ldst_st_p_d_pp_h.s c_ldst_st_p_p.s
c_ldst_st_p_p_mm.s c_ldst_st_p_p_pp.s
c_ldstidxl_ld_dr_b.s
c_ldstidxl_ld_dr_h.s
c_ldstidxl_ld_dr_xb.s
c_ldstidxl_ld_dr_xh.s
c_ldstidxl_ld_dreg.s
c_ldstidxl_ld_preg.s
c_ldstidxl_st_dr_b.s
c_ldstidxl_st_dr_h.s
c_ldstidxl_st_dreg.s
c_ldstidxl_st_preg.s c_ldstii_ld_dr_h.s
c_ldstii_ld_dr_xh.s c_ldstii_ld_dreg.s
c_ldstii_ld_preg.s c_ldstii_st_dr_h.s
c_ldstii_st_dreg.s c_ldstii_st_preg.s
c_ldstiifp_ld_dreg.s
c_ldstiifp_ld_preg.s
c_ldstiifp_st_dreg.s
c_ldstiifp_st_preg.s
c_ldstpmod_ld_dr_hi.s
c_ldstpmod_ld_dr_lo.s
c_ldstpmod_ld_dreg.s
c_ldstpmod_ld_h_xh.s
c_ldstpmod_ld_lohi.s
c_ldstpmod_st_dr_hi.s
c_ldstpmod_st_dr_lo.s
c_ldstpmod_st_dreg.s
c_ldstpmod_st_lohi.s c_linkage.s
c_logi2op_alshft_mix.s
c_logi2op_arith_shft.s
c_logi2op_bitclr.s c_logi2op_bitset.s
c_logi2op_bittgl.s c_logi2op_bittst.s
c_logi2op_log_l_shft.s
c_logi2op_log_l_shft_astat.S
c_logi2op_log_r_shft.s
c_logi2op_log_r_shft_astat.S
c_logi2op_nbittst.s c_loopsetup_nested.s
c_loopsetup_nested_bot.s
c_loopsetup_nested_prelc.s
c_loopsetup_nested_top.s
c_loopsetup_overlap.s
c_loopsetup_preg_div2_lc0.s
c_loopsetup_preg_div2_lc1.s
c_loopsetup_preg_lc0.s
c_loopsetup_preg_lc1.s
c_loopsetup_preg_stld.s
c_loopsetup_prelc.s
c_loopsetup_topbotcntr.s
c_mmr_interr_ctl.s c_mmr_loop.S
c_mmr_loop_user_except.S
c_mmr_ppop_illegal_adr.S
c_mmr_ppopm_illegal_adr.S c_mmr_timer.S
c_mode_supervisor.S c_mode_user.S
c_mode_user_superivsor.S
c_multi_issue_dsp_ld_ld.s
c_multi_issue_dsp_ldst_1.s
c_multi_issue_dsp_ldst_2.s
c_progctrl_call_pcpr.s
c_progctrl_call_pr.s
c_progctrl_clisti_interr.S
c_progctrl_csync_mmr.S
c_progctrl_except_rtx.S
c_progctrl_excpt.S
c_progctrl_jump_pcpr.s
c_progctrl_jump_pr.s c_progctrl_nop.s
c_progctrl_raise_rt_i_n.S
c_progctrl_rts.s c_ptr2op_pr_neg_pr.s
c_ptr2op_pr_sft_2_1.s
c_ptr2op_pr_shadd_1_2.s
c_pushpopmultiple_dp.s
c_pushpopmultiple_dp_pair.s
c_pushpopmultiple_dreg.s
c_pushpopmultiple_preg.s
c_regmv_acc_acc.s c_regmv_dag_lz_dep.s
c_regmv_dr_acc_acc.s
c_regmv_dr_dep_nostall.s c_regmv_dr_dr.s
c_regmv_dr_imlb.s c_regmv_dr_pr.s
c_regmv_imlb_dep_nostall.s
c_regmv_imlb_dep_stall.s
c_regmv_imlb_dr.s c_regmv_imlb_imlb.s
c_regmv_imlb_pr.s
c_regmv_pr_dep_nostall.s
c_regmv_pr_dep_stall.s c_regmv_pr_dr.s
c_regmv_pr_imlb.s c_regmv_pr_pr.s
c_seq_ac_raise_mv.S
c_seq_ac_raise_mv_ppop.S
c_seq_ac_regmv_pushpop.S
c_seq_dec_raise_pushpop.S
c_seq_ex1_brcc_mv_pop.S
c_seq_ex1_call_mv_pop.S
c_seq_ex1_j_mv_pop.S
c_seq_ex1_raise_brcc_mv_pop.S
c_seq_ex1_raise_call_mv_pop.S
c_seq_ex1_raise_j_mv_pop.S
c_seq_ex2_brcc_mp_mv_pop.S
c_seq_ex2_mmr_mvpop.S
c_seq_ex2_mmrj_mvpop.S
c_seq_ex2_raise_mmr_mvpop.S
c_seq_ex2_raise_mmrj_mvpop.S
c_seq_ex3_ls_brcc_mvp.S
c_seq_ex3_ls_mmr_mvp.S
c_seq_ex3_ls_mmrj_mvp.S
c_seq_ex3_raise_ls_mmrj_mvp.S
c_seq_wb_cs_lsmmrj_mvp.S
c_seq_wb_raisecs_lsmmrj_mvp.S
c_seq_wb_rti_lsmmrj_mvp.S
c_seq_wb_rtn_lsmmrj_mvp.S
c_seq_wb_rtx_lsmmrj_mvp.S c_ujump.s
cc-alu.S cc-astat-bits.s cc0.s cc1.s
cc5.S cec-exact-exception.S cec-ifetch.S
cec-multi-pending.S cec-no-snen-reti.S
cec-non-operating-env.s cec-raise-reti.S
cec-snen-reti.S cec-syscfg-ssstep.S
cec-system-call.S cir.s cir1.s cli-sti.s
cmpacc.s cmpdreg.S compare.s
conv_enc_gen.s cycles.s d0.s d1.s d2.s
dbg_brprd_ntkn_src_kill.S
dbg_brtkn_nprd_src_kill.S
dbg_jmp_src_kill.S dbg_tr_basic.S
dbg_tr_simplejp.S dbg_tr_tbuf0.S
dbg_tr_umode.S disalnexcpt_implicit.S
div0.s divq.s dotproduct.s dotproduct2.s
double_prec_mult.s dsp_a4.s dsp_a7.s
dsp_a8.s dsp_d0.s dsp_d1.s dsp_neg.S
dsp_s1.s e0.s edn_snafu.s
eu_dsp32mac_s.s events.s f221.s fact.s
fir.s fsm.s greg2.s hwloop-bits.S
hwloop-branch-in.s hwloop-branch-out.s
hwloop-lt-bits.s hwloop-nested.s i0.s
iir.s issue103.s issue109.s issue112.s
issue113.s issue117.s issue118.s
issue119.s issue121.s issue123.s
issue124.s issue125.s issue126.s
issue127.s issue129.s issue139.S
issue140.S issue142.s issue144.s
issue146.S issue175.s issue205.s
issue257.s issue272.S issue83.s
issue89.s l0.s l0shift.s l2_loop.s
link-2.s link.s lmu_cplb_multiple0.S
lmu_cplb_multiple1.S lmu_excpt_align.S
lmu_excpt_default.S lmu_excpt_illaddr.S
lmu_excpt_prot0.S lmu_excpt_prot1.S
load.s logic.s loop_snafu.s
loop_strncpy.s lp0.s lp1.s lsetup.s
m0boundary.s m1.S m10.s m11.s m12.s
m13.s m14.s m15.s m16.s m17.s m2.s m3.s
m4.s m5.s m6.s m7.s m8.s m9.s
mac2halfreg.S math.s max_min_flags.s
mc_s2.s mdma-32bit-1d-neg-count.c
mdma-32bit-1d.c mdma-8bit-1d-neg-count.c
mdma-8bit-1d.c mdma-skel.h mem3.s
mmr-exception.s move.s msa_acp_5.10.S
msa_acp_5.12_1.S msa_acp_5.12_2.S
msa_acp_5_10.s mult.s neg-2.S neg-3.S
neg.S nshift.s pr.s push-pop-multiple.s
push-pop.s pushpopreg_1.s quadaddsub.s
random_0001.s random_0002.S
random_0003.S random_0004.S
random_0005.S random_0006.S
random_0007.S random_0008.S
random_0009.S random_0010.S
random_0011.S random_0012.S
random_0013.S random_0031.S
random_0033.S random_0034.S run-tests.sh
s0.s s1.s s10.s s11.s s12.s s13.s s14.s
s15.s s16.s s17.s s18.s s19.s s2.s s20.s
s21.s s3.s s30.s s4.s s5.s s6.s s7.s
s8.s s9.s saatest.s se_all16bitopcodes.S
se_all32bitopcodes.S
se_all32bitopcodes.lds
se_brtarget_stall.S se_bug_ui.S
se_bug_ui2.S se_bug_ui3.S
se_cc2stat_haz.S se_cc_kill.S se_cof.S
se_event_quad.S se_excpt_dagprotviol.S
se_excpt_ifprotviol.S se_excpt_ssstep.S
se_illegalcombination.S se_kill_wbbr.S
se_kills2.S se_loop_disable.S
se_loop_kill.S se_loop_kill_01.S
se_loop_kill_dcr.S se_loop_kill_dcr_01.S
se_loop_lr.S se_loop_mv2lb_stall.S
se_loop_mv2lc.S se_loop_mv2lc_stall.S
se_loop_mv2lt_stall.S se_loop_nest_ppm.S
se_loop_nest_ppm_1.S
se_loop_nest_ppm_2.S se_loop_ppm.S
se_loop_ppm_1.S se_loop_ppm_int.S
se_lsetup_kill.S se_misaligned_fetch.S
se_more_ret_haz.S se_mv2lp.S
se_oneins_zoff.S se_popkill.S
se_regmv_usp_sysreg.S se_rets_hazard.s
se_rts_rti.S se_ssstep_dagprotviol.S
se_ssync.S se_stall_if2.S
se_undefinedinstruction1.S
se_undefinedinstruction2.S
se_undefinedinstruction3.S
se_undefinedinstruction4.S
se_usermode_protviol.S seqstat.s sign.s
simple0.s sri.s stk.s stk2.s stk3.s
stk4.s stk5.s stk6.s syscfg.s tar10622.s
test-dma.h test.h testset.s testset2.s
testutils.inc unlink.S up0.s usp.S
vec-abs-2.S vec-abs-3.S vec-abs.S
vec-neg-2.S vec-neg-3.S vec-neg.S
vecadd.s vit_max.s viterbi2.s wtf.s x1.s
zcall.s zeroflagrnd.s
Log message:
sim: bfin: import testsuite
Now that the common sim testsuite code supports .S and .c files, we
can import the Blackfin testsuite. There are about ~800 tests here,
so I'm only attaching a compressed patch of them. Other than adding
files to sim/testsuite/sim/bfin/, the sim/configure.tgt file was
updated to mark Blackfin as having a testsuite, and sim/configure
regenerated.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/ChangeLog.diff?cvsroot=src&r1=1.151&r2=1.152
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/configure.diff?cvsroot=src&r1=1.36&r2=1.37
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/configure.tgt.diff?cvsroot=src&r1=1.3&r2=1.4
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/10272_small.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/10436.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/10622.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/10742.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/10799.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/11080.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/7641.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/ChangeLog.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/PN_generator.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a0.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a0shift.S.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a1.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a10.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a11.S.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a12.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a2.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a20.S.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a21.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a22.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a23.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a24.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a25.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a26.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a3.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a30.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a4.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a5.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a6.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a7.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a8.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/a9.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/abs-2.S.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/abs-3.S.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/abs-4.S.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/abs.S.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/abs_acc.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/acc-rot.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/acp5_19.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/acp5_4.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/add_imm7.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/add_shift.S.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/add_sub_acc.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/addsub_flags.S.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/algnbug1.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/algnbug2.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/allinsn.exp.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/argc.c.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/ashift.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/ashift_flags.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/b0.S.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/b1.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/b2.S.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/brcc.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/brevadd.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/byteop16m.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/byteop16p.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/byteop1p.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/byteop2p.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/byteop3p.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/byteunpack.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_alu2op_arith_r_sft.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_alu2op_conv_b.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_alu2op_conv_h.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_alu2op_conv_mix.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_alu2op_conv_neg.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_alu2op_conv_toggle.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_alu2op_conv_xb.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_alu2op_conv_xh.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_alu2op_divq.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_alu2op_divs.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_alu2op_log_l_sft.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_alu2op_log_r_sft.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_alu2op_shadd_1.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_alu2op_shadd_2.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_br_preg_killed_ac.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_br_preg_killed_ex1.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_br_preg_stall_ac.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_br_preg_stall_ex1.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_brcc_bp1.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_brcc_bp2.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_brcc_bp3.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_brcc_bp4.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_brcc_brf_bp.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_brcc_brf_brt_bp.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_brcc_brf_brt_nbp.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_brcc_brf_fbkwd.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_brcc_brf_nbp.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_brcc_brt_bp.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_brcc_brt_nbp.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_brcc_kills_dhits.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_brcc_kills_dmiss.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_cactrl_iflush_pr.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_cactrl_iflush_pr_pp.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_calla_ljump.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_calla_subr.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_cc2dreg.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_cc2stat_cc_ac.S.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_cc2stat_cc_an.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_cc2stat_cc_aq.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_cc2stat_cc_av0.S.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_cc2stat_cc_av1.S.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_cc2stat_cc_az.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_cc_flag_ccmv_depend.S.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft_s1.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft_sn.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft_s1.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/bfin/c_cc_regmvlogi_mvbrsft_sn.S.diff?cvsroot=src&r1=NONE&r2=1.1
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