[binutils-gdb] RISC-V: Linux signal frame support.

[Jim Wilson <wilson at sourceware dot org>]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=8a61382623e271fe2df0fe8f7558ea545db8b561

commit 8a61382623e271fe2df0fe8f7558ea545db8b561
Author: Jim Wilson <jimw@sifive.com>
Date:   Fri Oct 26 10:29:46 2018 -0700

    RISC-V: Linux signal frame support.
    
    Make riscv_isa_flen available to the linux native code, and clean up duplicate
    comments.
    
    	gdb/
    	* riscv-tdep.c (riscv_isa_xlen): Refer to riscv-tdep.h comment.
    	(riscv_isa_flen): Likewise.  Drop static.
    	* riscv-tdep.h (riscv_isa_xlen): Move riscv-tdep.c comment to here.
    	(riscv_isa_flen): Likewise.

Diff:
---
 gdb/ChangeLog    |  7 +++++++
 gdb/riscv-tdep.c | 11 +++--------
 gdb/riscv-tdep.h | 11 ++++++++++-
 3 files changed, 20 insertions(+), 9 deletions(-)

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 4376263..4d068ee 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,10 @@
+2018-10-26  Jim Wilson  <jimw@sifive.com>
+
+	* riscv-tdep.c (riscv_isa_xlen): Refer to riscv-tdep.h comment.
+	(riscv_isa_flen): Likewise.  Drop static.
+	* riscv-tdep.h (riscv_isa_xlen): Move riscv-tdep.c comment to here.
+	(riscv_isa_flen): Likewise.  Declare.
+
 2018-10-26  Edjunior Barbosa Machado  <emachado@linux.vnet.ibm.com>
 	    Pedro Franco de Carvalho  <pedromfc@linux.ibm.com>
 
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index e4b35a0..4b5f38a 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -349,9 +349,7 @@ riscv_has_feature (struct gdbarch *gdbarch, char feature)
   return (misa & (1 << (feature - 'A'))) != 0;
 }
 
-/* Return the width in bytes  of the general purpose registers for GDBARCH.
-   Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
-   RV128.  */
+/* See riscv-tdep.h.  */
 
 int
 riscv_isa_xlen (struct gdbarch *gdbarch)
@@ -370,12 +368,9 @@ riscv_isa_xlen (struct gdbarch *gdbarch)
     }
 }
 
-/* Return the width in bytes of the floating point registers for GDBARCH.
-   If this architecture has no floating point registers, then return 0.
-   Possible values are 4, 8, or 16 for depending on which of single, double
-   or quad floating point support is available.  */
+/* See riscv-tdep.h.  */
 
-static int
+int
 riscv_isa_flen (struct gdbarch *gdbarch)
 {
   if (riscv_has_feature (gdbarch, 'Q'))
diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
index e04e728..2cb51b1 100644
--- a/gdb/riscv-tdep.h
+++ b/gdb/riscv-tdep.h
@@ -84,9 +84,18 @@ struct gdbarch_tdep
   struct type *riscv_fpreg_q_type;
 };
 
-/* Return the width in bytes of the general purpose registers for GDBARCH.  */
+
+/* Return the width in bytes  of the general purpose registers for GDBARCH.
+   Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
+   RV128.  */
 extern int riscv_isa_xlen (struct gdbarch *gdbarch);
 
+/* Return the width in bytes of the floating point registers for GDBARCH.
+   If this architecture has no floating point registers, then return 0.
+   Possible values are 4, 8, or 16 for depending on which of single, double
+   or quad floating point support is available.  */
+extern int riscv_isa_flen (struct gdbarch *gdbarch);
+
 /* Single step based on where the current instruction will take us.  */
 extern std::vector<CORE_ADDR> riscv_software_single_step
   (struct regcache *regcache);