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Re: [PATCH] simulator for mips3264
"Eric M. Christopher" <echristo@redhat.com> writes:
> > (3) why did you add clo/clz in mips.igen? I know there are some
> > non-true-mips32/mips64 CPUs which implement them... but they also
> > implement madd/maddu/msub/msubu. Any argument that puts these in
> > mips.igen also puts the rest, as far as I can see.
> >
>
> Ok. I can do this...
>
> > Personally, if I were doing this ("oh wait, we did, but I've not
> > had time to go back and submit it all yet!" 8-) I'd put the new
> > mips32/mips64 instructions into mips.igen, since they're neither
> > particular chip-specific and they're not an ASE either.
> >
>
> Or this. Pick one :)
The latter. Throw them all into mips.igen, please.
> > (4) you're missing dclo + dclz.
>
> Got one for me? ;)
i've included ours below for reference. I've not tried to drop them
into the current GDB sources, and not looked at all our local changes
to the infrastructure in a while; i'd guess they probably won't
compile as-is. 8-)
The code below was written by Ed Satterthwaite, one of my coworkers
(who also has an assignment on file, of course 8-).
Actually, looking at this more closely points out a couple of issues:
* clo, clz, dclo, dclz all operate on input 'rs'. (Yours used input
from 'rt'. Like you said, you were working from an old version of
the MIPS32 spec. 8-)
* At some point, the new instructions that you've added should have
the appropriate tracing machinery put in place. I don't think this
has to be fixed Right Now, but it should be fixed at some point.
chris
========
011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
"dclo r<RD>,r<RS>"
*mips64:
{
unsigned64 temp = GPR[RS];
unsigned32 i;
unsigned64 mask;
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT1 (GPR[RS]);
for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
{
if ((temp & mask) == 0)
break;
mask >>= 1;
}
GPR[RD] = EXTEND32 (i);
TRACE_ALU_RESULT (GPR[RD]);
}
011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
"dclz r<RD>,r<RS>"
*mips64:
{
unsigned64 temp = GPR[RS];
unsigned32 i;
unsigned64 mask;
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT1 (GPR[RS]);
for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
{
if ((temp & mask) != 0)
break;
mask >>= 1;
}
GPR[RD] = EXTEND32 (i);
TRACE_ALU_RESULT (GPR[RD]);
}