Re: [RFA] Basic structure to describe register formats

[Andrew Cagney <ac131313 at cygnus dot com>]

> You mean - 32:r1?
>> 
>> I think the ``4'' indicates 4*2 hex digits.  Digit pairs ordered either 
>> big or little endian.  Yes it could be bits, however, the value would 
>> always need to be divisible by 8.
> 
> 
> No, I don't think it needs to be divisible by 8.  If it did I wouldn't
> feel the need to represent the 8.
> 
> For instance:
>  - ia64 has 1-bit registers that we currently transmit as either bytes
> or words, IIRC.


Here, I don't think we're worried about how many bits a register 
occupies.  Rather, how that register is is represented when ``spilt'' 
into memory (to use the way the ia64 describes its in memory FP register 
format).  It is that ``spilt'' format, transmitted as ascii encoded hex 
digit pairs, that is being described.

A target with registers one bit in size could either spill each register 
into individual byte/word/... or combine them into a single word.  For 
the latter, I think we'd end up with something like ``8:f0f1f2f3f4f5'',


>  - someone mentioned recently working on a non-8-bit target for GDB,
> but he wasn't quite ready to contribute it.


Yes.


> But it will be divisible by 8 for now, so we'll just ignore that for
> the moment.


:-)

Andrew