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Re:[PATCH/RFA] h8300 Multiple changes to gdb/sim-stage5
- From: Andrew Volkov <Andrew dot Volkov at transas dot com>
- To: gdb-patches at sources dot redhat dot com
- Date: Thu, 16 May 2002 16:16:05 +0400
- Subject: Re:[PATCH/RFA] h8300 Multiple changes to gdb/sim-stage5
Splitting after suggestions of Andrew Cagney.
Andrey Volkov
2002-05-15 Andrey Volkov <avolkov@sources.redhat.com>
* gdb/config/h8300/tm-h8300.h: Add support of EXR register
* gdb/h8300-tdep.c: Ditto.
* sim/h8300/compile.c: Ditto.
* sim/h8300/inst.h: Ditto.
diff -ruN gdb.old/gdb/config/h8300/tm-h8300.h
gdb/gdb/config/h8300/tm-h8300.h
--- gdb.old/gdb/config/h8300/tm-h8300.h Tue Jan 29 07:42:36 2002
+++ gdb/gdb/config/h8300/tm-h8300.h Wed May 15 20:28:57 2002
@@ -100,7 +100,7 @@
#define REGISTER_SIZE 4
-#define NUM_REGS 13
+#define NUM_REGS 14
#define REGISTER_BYTES (NUM_REGS * 4)
@@ -137,7 +137,7 @@
Entries beyond the first NUM_REGS are ignored. */
#define REGISTER_NAMES \
- {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "sp",
"ccr","pc","cycles","tick","inst"}
+ {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "sp",
"ccr","pc","cycles","tick","inst",""}
/* An array of names of registers. */
@@ -157,6 +157,7 @@
#define SP_REGNUM 7 /* Contains address of top of stack */
#define CCR_REGNUM 8 /* Contains processor status */
#define PC_REGNUM 9 /* Contains program counter */
+#define EXR_REGNUM 11 /* Contains processor status */
/* Extract from an array REGBUF containing the (raw) register state
a function return value of type TYPE, and copy that, in virtual format,
@@ -272,7 +273,7 @@
#define GDB_TARGET_IS_H8300
-#define NUM_REALREGS 10
+#define NUM_REALREGS (h8300smode?11:10)
#define NOP { 0x01, 0x80} /* A sleep insn */
#define BELIEVE_PCC_PROMOTION 1
diff -ruN gdb.old/gdb/h8300-tdep.c gdb/gdb/h8300-tdep.c
--- gdb.old/gdb/h8300-tdep.c Wed May 15 19:52:44 2002
+++ gdb/gdb/h8300-tdep.c Wed May 15 20:28:57 2002
@@ -38,8 +38,8 @@
extern int h8300hmode, h8300smode;
-#undef NUM_REGS
-#define NUM_REGS 11
+#undef NUM_REGS
+#define NUM_REGS (h8300smode?12:11)
#define UNSIGNED_SHORT(X) ((X) & 0xffff)
@@ -61,7 +61,7 @@
static char *h8300h_register_names[] =
{"er0", "er1", "er2", "er3", "er4", "er5", "er6",
- "sp", "ccr", "pc", "cycles", "tick", "inst"};
+ "sp", "ccr","pc", "cycles", "exr", "tick", "inst"};
char **h8300_register_names = original_register_names;
@@ -870,6 +870,20 @@
if ((Z | (N ^ V)) == 1)
printf_unfiltered ("<= ");
}
+
+ if (regno == EXR_REGNUM && h8300smode)
+ {
+ /* EXR register */
+ unsigned char b[REGISTER_SIZE];
+ unsigned char l;
+ read_relative_register_raw_bytes (regno, b);
+ l = b[REGISTER_VIRTUAL_SIZE (EXR_REGNUM) - 1];
+ printf_unfiltered ("\t");
+ printf_unfiltered ("T-%d - - - ", (l & 0x80) != 0);
+ printf_unfiltered ("I2-%d ", (l & 4) != 0);
+ printf_unfiltered ("I1-%d ", (l & 2) != 0);
+ printf_unfiltered ("I0-%d", (l & 1) != 0);
+ }
}
void
diff -ruN gdb.old/sim/h8300/compile.c gdb/sim/h8300/compile.c
--- gdb.old/sim/h8300/compile.c Wed May 15 20:27:13 2002
+++ gdb/sim/h8300/compile.c Wed May 15 20:32:22 2002
@@ -67,6 +67,7 @@
#define OP_CCR 7
#define OP_IMM 8
#define OP_ABS 10
+#define OP_EXR 11
#define h8_opcodes ops
#define DEFINE_TABLE
#include "opcode/h8300.h"
@@ -84,6 +85,9 @@
#define BUILDSR() cpu.ccr = (I << 7) | (UI << 6)| (H<<5) | (U<<4) | \
(N << 3) | (Z << 2) | (V<<1) | C;
+#define BUILDEXR() \
+ if( h8300smode ) cpu.exr = ( trace<<7 ) | intMask;
+
#define GETSR() \
c = (cpu.ccr >> 0) & 1;\
v = (cpu.ccr >> 1) & 1;\
@@ -94,6 +98,11 @@
ui = ((cpu.ccr >> 6) & 1);\
intMaskBit = (cpu.ccr >> 7) & 1;
+#define GETEXR() \
+ if( h8300smode ) { \
+ trace = (cpu.exr >> 7) & 1;\
+ intMask = cpu.exr & 7; }
+
#ifdef __CHAR_IS_SIGNED__
#define SEXTCHAR(x) ((char) (x))
#endif
@@ -412,6 +421,10 @@
{
p->type = OP_CCR;
}
+ else if (x & EXR)
+ {
+ p->type = OP_EXR;
+ }
else
printf ("Hmmmm %x", x);
@@ -946,6 +959,7 @@
int bit;
int pc;
int c, nz, v, n, u, h, ui, intMaskBit;
+ int trace, intMask;
int oldmask;
init_pointers ();
@@ -969,6 +983,8 @@
abort ();
GETSR ();
+ GETEXR ();
+
oldmask = cpu.mask;
if (!h8300hmode)
cpu.mask = 0xffff;
@@ -1180,21 +1196,49 @@
#define GET_CCR(x) BUILDSR();x = cpu.ccr
+#define GET_EXR(x) BUILDEXR();x = cpu.exr
case O (O_ANDC, SB):
- GET_CCR (rd);
+ if(code->dst.type==OP_CCR)
+ {
+ GET_CCR (rd);
+ }
+ else if(code->dst.type==OP_EXR && h8300smode)
+ {
+ GET_EXR (rd);
+ }
+ else
+ goto illegal;
ea = code->src.literal;
res = rd & ea;
goto setc;
case O (O_ORC, SB):
- GET_CCR (rd);
+ if(code->dst.type==OP_CCR)
+ {
+ GET_CCR (rd);
+ }
+ else if(code->dst.type==OP_EXR && h8300smode)
+ {
+ GET_EXR (rd);
+ }
+ else
+ goto illegal;
ea = code->src.literal;
res = rd | ea;
goto setc;
case O (O_XORC, SB):
- GET_CCR (rd);
+ if(code->dst.type==OP_CCR)
+ {
+ GET_CCR (rd);
+ }
+ else if(code->dst.type==OP_EXR && h8300smode)
+ {
+ GET_EXR (rd);
+ }
+ else
+ goto illegal;
ea = code->src.literal;
res = rd ^ ea;
goto setc;
@@ -1541,6 +1585,7 @@
goto next;
default:
+ illegal:
cpu.state = SIM_STATE_STOPPED;
cpu.exception = SIGILL;
goto end;
@@ -1549,8 +1594,19 @@
abort ();
setc:
- cpu.ccr = res;
- GETSR ();
+ if(code->dst.type==OP_CCR)
+ {
+ cpu.ccr = res;
+ GETSR ();
+ }
+ else if(code->dst.type==OP_EXR && h8300smode)
+ {
+ cpu.exr = res;
+ GETEXR ();
+ }
+ else
+ goto illegal;
+
goto next;
condtrue:
@@ -1730,6 +1786,7 @@
cpu.pc = pc;
BUILDSR ();
+ BUILDEXR();
cpu.mask = oldmask;
signal (SIGINT, prev);
}
@@ -1802,6 +1859,7 @@
#define PC_REGNUM 9 /* Contains program counter */
#define CYCLE_REGNUM 10
+#define EXR_REGNUM 11 /* Contains extended processor status */
#define INST_REGNUM 11
#define TICK_REGNUM 12
@@ -1841,6 +1899,9 @@
case CCR_REGNUM:
cpu.ccr = intval;
break;
+ case EXR_REGNUM:
+ cpu.exr = intval;
+ break;
case CYCLE_REGNUM:
cpu.cycles = longval;
break;
@@ -1868,12 +1929,17 @@
init_pointers ();
+ if(!h8300smode && rn >=EXR_REGNUM)
+ rn++;
switch (rn)
{
default:
abort ();
case CCR_REGNUM:
v = cpu.ccr;
+ break;
+ case EXR_REGNUM:
+ v = cpu.exr;
break;
case PC_REGNUM:
v = cpu.pc;
diff -ruN gdb.old/sim/h8300/inst.h gdb/sim/h8300/inst.h
--- gdb.old/sim/h8300/inst.h Wed May 15 20:27:13 2002
+++ gdb/sim/h8300/inst.h Wed May 15 20:28:57 2002
@@ -32,6 +32,7 @@
R_ZERO,
R_PC,
R_CCR,
+ R_EXR,
R_HARD_0,
R_LAST,
} reg_type;
@@ -73,7 +74,7 @@
unsigned int regs[9];
int pc;
int ccr;
-
+ int exr;
unsigned char *memory;
unsigned char *eightbit;