This is the mail archive of the
gdb-patches@sources.redhat.com
mailing list for the GDB project.
ARM simulator: Improve checks for valid XScale instructions
- From: Nick Clifton <nickc at cambridge dot redhat dot com>
- To: gdb-patches at sources dot redhat dot com
- Date: 05 Jul 2002 15:11:53 +0100
- Subject: ARM simulator: Improve checks for valid XScale instructions
Hi Guys,
I am applying the patch below to improve the checks in the ARM
sim-based simulator for valid XScale instructions. Without these
checks some invalid bit patterns were being executed as if they were
valid XScale instructions.
Cheers
Nick
2002-07-05 Nick Clifton <nickc@cambridge.redhat.com>
* armemu.c (ARMul_Emulate32): Add more tests for valid MIA, MIAPH
and MIAxy instructions.
Index: sim/arm/armemu.c
===================================================================
RCS file: /cvs/src/src/sim/arm/armemu.c,v
retrieving revision 1.27
diff -c -3 -p -w -r1.27 armemu.c
*** sim/arm/armemu.c 27 May 2002 14:11:55 -0000 1.27
--- sim/arm/armemu.c 5 Jul 2002 14:09:38 -0000
*************** check_PMUintr:
*** 3366,3374 ****
switch (BITS (18, 19))
{
case 0x0:
{
! /* XScale MIA instruction. Signed multiplication of two 32 bit
! values and addition to 40 bit accumulator. */
long long Rm = state->Reg[MULLHSReg];
long long Rs = state->Reg[MULACCReg];
--- 3366,3375 ----
switch (BITS (18, 19))
{
case 0x0:
+ if (BITS (4, 11) == 1 && BITS (16, 17) == 0)
{
! /* XScale MIA instruction. Signed multiplication of
! two 32 bit values and addition to 40 bit accumulator. */
long long Rm = state->Reg[MULLHSReg];
long long Rs = state->Reg[MULACCReg];
*************** check_PMUintr:
*** 3377,3386 ****
if (Rs & (1 << 31))
Rs -= 1ULL << 32;
state->Accumulator += Rm * Rs;
- }
goto donext;
case 0x2:
{
/* XScale MIAPH instruction. */
ARMword t1 = state->Reg[MULLHSReg] >> 16;
--- 3378,3389 ----
if (Rs & (1 << 31))
Rs -= 1ULL << 32;
state->Accumulator += Rm * Rs;
goto donext;
+ }
+ break;
case 0x2:
+ if (BITS (4, 11) == 1 && BITS (16, 17) == 0)
{
/* XScale MIAPH instruction. */
ARMword t1 = state->Reg[MULLHSReg] >> 16;
*************** check_PMUintr:
*** 3407,3416 ****
if (t5 & (1 << 31))
t5 -= 1ULL << 32;
state->Accumulator += t5;
- }
goto donext;
case 0x3:
{
/* XScale MIAxy instruction. */
ARMword t1;
--- 3410,3421 ----
if (t5 & (1 << 31))
t5 -= 1ULL << 32;
state->Accumulator += t5;
goto donext;
+ }
+ break;
case 0x3:
+ if (BITS (4, 11) == 1)
{
/* XScale MIAxy instruction. */
ARMword t1;
*************** check_PMUintr:
*** 3436,3443 ****
if (t5 & (1 << 31))
t5 -= 1ULL << 32;
state->Accumulator += t5;
- }
goto donext;
default:
break;
--- 3441,3449 ----
if (t5 & (1 << 31))
t5 -= 1ULL << 32;
state->Accumulator += t5;
goto donext;
+ }
+ break;
default:
break;