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Re: [WIP/RFC] MIPS registers overhaul
- From: Andrew Cagney <ac131313 at redhat dot com>
- To: cgd at broadcom dot com
- Cc: Kevin Buettner <kevinb at redhat dot com>,gdb-patches at sources dot redhat dot com
- Date: Tue, 17 Jun 2003 10:27:09 -0400
- Subject: Re: [WIP/RFC] MIPS registers overhaul
- References: <1030510002453.ZM3880@localhost.localdomain> <3EBD6131.30209@redhat.com> <1030514220025.ZM10373@localhost.localdomain> <3EC461C1.1080104@redhat.com> <mailpost.1053057614.17325@news-sj1-1> <yov5znlma5s9.fsf@broadcom.com> <mailpost.1053123913.16634@news-sj1-1> <yov5wugqa4m8.fsf@broadcom.com> <3ECA8EC6.6030405@redhat.com> <yov5llx1mkab.fsf@broadcom.com> <3EECAB89.10609@redhat.com> <yov5wuflwzx4.fsf@ldt-sj3-010.sj.broadcom.com> <3EEE2B85.6030207@redhat.com> <mailpost.1055796186.4097@news-sj1-1> <yov5znkhe1m7.fsf@ldt-sj3-010.sj.broadcom.com>
Careful. If the ABI is o32, and FR == 0/..., then there should be
only 16 floating point registers in use. The original MIPS 1, and
r5900 ABIs would both allow use of all 32 32 bit floating point
registers.
I don't know that that is correct, at least about the "original MIPS
1" behaviour.
Sigh, yes: B 3.3 Formatted Operand Layout of [3.2]:
FPU instructions that operate on formatted operand values specify the
floating-point register (FPR) that holds a value. An FPR is not
necessarily the same as a CP1 general register because an FPR is 64 bits
wide; if this is wider than the CP1 general registers, an aligned set of
adjacent CP1 general registers is used as the FPR. The 32-bit register
model provides 16 FPRs specified by the even CP1 general register
numbers. The 64-bit register model provides 32 FPRs, one per CP1 general
register. Operands that are only 32 bits wide (W and S formats), use
only half the space in an FPR. The FPR organization and the way that
operand data is stored in them is shown in the following figures. A
summary of the data transfer instructions can be found in section B 6.1
on page B-19.
The key bit being that the terminology differentaties between a 32 bit
CP1 register and a 64 bit FPR.
This also suggests a better way of representing the registers to the user:
MIPS I:
$cp0, $cp1, ...: 32/64 bit raw co-processor registers
MIPS I:
$fp0, $fp2, ...: 64 bit co-processor registers
note that these are little word ordered
and contain 32 and 64 bit float values
(This was suggested to me in a second hand
off line discussion :-()
MIPS III:
$fp0, $fp1, ...: 64 bit floating point registers
Andrew