This is the mail archive of the
gdb-patches@sources.redhat.com
mailing list for the GDB project.
[RFA] new tests for h8 sim
- From: Michael Snyder <msnyder at redhat dot com>
- To: Kazu Hirata <kazu at cs dot umass dot edu>, dvenkat at noida dot hcltech dot com, gdb-patches at sources dot redhat dot com
- Date: Tue, 22 Jul 2003 12:37:54 -0700
- Subject: [RFA] new tests for h8 sim
A few test extensions and enhancements.
2003-07-22 Michael Snyder <msnyder@redhat.com>
* cmpw.s: Add test for less-than-zero immediate.
* shll.s: Test for shll reg, reg.
* shlr.s: Test for shlr reg, reg.
Index: shll.s
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/h8300/shll.s,v
retrieving revision 1.1
diff -p -r1.1 shll.s
*** shll.s 13 Apr 2003 16:44:57 -0000 1.1
--- shll.s 22 Jul 2003 19:36:17 -0000
*************** shll_b_reg8_4:
*** 90,95 ****
--- 90,117 ----
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
+
+ shll_b_reg8_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #5, r0h
+ shll.b r0h, r0l ; shift left logical by register value
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+ test_h_gr16 0x05a0 r0 ; 1010 0101 -> 1010 0000
+ test_h_gr32 0xa5a505a0 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
.endif
.if (sim_cpu) ; Not available in h8300 mode
*************** shll_w_reg16_8:
*** 181,186 ****
--- 203,230 ----
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
+
+ shll_w_reg16_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #5, r0h
+ shll.w r0h, r0 ; shift left logical by register value
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+ test_h_gr16 0xb4a0 r0 ; 1010 0101 1010 0101 -> 1011 0100 1010 0000
+ test_h_gr32 0xa5a5b4a0 er0
+
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
.endif
shll_l_reg32_1:
*************** shll_l_reg32_16:
*** 294,299 ****
--- 338,366 ----
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ shll_l_reg32_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #5, r1l
+ shll.l r1l, er0 ; shift left logical by register value
+
+ test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_set
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 1011 0100 1011 0100 1011 0100 1010 0000
+ test_h_gr32 0xb4b4b4a0 er0
+
+ test_h_gr32 0xa5a5a505 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
Index: shlr.s
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/h8300/shlr.s,v
retrieving revision 1.2
diff -p -r1.2 shlr.s
*** shlr.s 14 May 2003 21:07:55 -0000 1.2
--- shlr.s 22 Jul 2003 19:36:18 -0000
*************** shlr_b_reg8_4:
*** 691,696 ****
--- 691,718 ----
test_gr_a5a5 6
test_gr_a5a5 7
+ shlr_b_reg8_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #5, r0h
+ shlr.b r0h, r0l ; shift right logical by register value
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr16 0x0505 r0 ; 1010 0101 -> 0000 0101
+ test_h_gr32 0xa5a50505 er0
+ test_gr_a5a5 1 ; Make sure other general regs not disturbed
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
shlr_b_ind_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
*************** shlr_w_reg16_4:
*** 1685,1690 ****
--- 1707,1734 ----
test_gr_a5a5 6
test_gr_a5a5 7
+ shlr_w_reg16_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #5, r1l
+ shlr.w r1l, r0 ; shift right logical by register value
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+
+ test_h_gr16 0x052d r0 ; 1010 0101 1010 0101 -> 0000 0101 0010 1101
+ test_h_gr32 0xa5a5052d er0
+ test_h_gr32 0xa5a5a505 er1
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
shlr_w_ind_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
*************** shlr_l_reg32_4:
*** 3023,3028 ****
--- 3067,3095 ----
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
+ shlr_l_reg32_reg8:
+ set_grs_a5a5 ; Fill all general regs with a fixed pattern
+ set_ccr_zero
+
+ mov #5, r1l
+ shlr.l r1l, er0 ; shift right logical by value of register
+
+ test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
+ test_zero_clear
+ test_ovf_clear
+ test_neg_clear
+ ; 1010 0101 1010 0101 1010 0101 1010 0101
+ ; -> 0000 0101 0010 1101 0010 1101 0010 1101
+ test_h_gr32 0x052d2d2d er0
+ test_h_gr32 0xa5a5a505 er1
+
+ test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
Index: cmpw.s
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/h8300/cmpw.s,v
retrieving revision 1.1
diff -p -r1.1 cmpw.s
*** cmpw.s 14 May 2003 21:07:55 -0000 1.1
--- cmpw.s 22 Jul 2003 19:36:18 -0000
*************** cmp_w_imm16: ; cmp.w immediate not ava
*** 48,54 ****
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
! ;; cmp.w #xx:8,Rd
cmp.w #0xa5a5, r0 ; Immediate 16-bit operand
beq eqi
fail
--- 48,54 ----
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
! ;; cmp.w #xx:16,Rd
cmp.w #0xa5a5, r0 ; Immediate 16-bit operand
beq eqi
fail
*************** gti:
*** 71,76 ****
--- 71,92 ----
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
+
+ cmp_w_imm16_less_than_zero: ; Test for less-than-zero immediate
+ set_grs_a5a5
+ ;; cmp.w #xx:16, Rd, where #xx < 0 (ie. #xx > 0x7fff).
+ sub.w r0, r0
+ cmp.w #0x8001, r0
+ bls ltz
+ fail
+ ltz: test_gr_a5a5 1
+ test_gr_a5a5 2
+ test_gr_a5a5 3
+ test_gr_a5a5 4
+ test_gr_a5a5 5
+ test_gr_a5a5 6
+ test_gr_a5a5 7
+
.endif
cmp_w_reg: