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[PATCH] New sh-sim tests for MAC.W, MAC.L (sim/1116)
- From: Michael Snyder <msnyder at redhat dot com>
- To: gdb-patches at sources dot redhat dot com, ShrinivasA at KPITCummins dot com
- Date: Mon, 11 Aug 2003 12:36:03 -0700
- Subject: [PATCH] New sh-sim tests for MAC.W, MAC.L (sim/1116)
Committing these new tests to sim/testsuite/sim/sh (adapted from the
sh64 tests).
2003-08-11 Michael Snyder <msnyder@redhat.com>
* macl.s: New file.
* macw.s: New file.
* allinsn.exp: Add new tests for mac.w and mac.l.
Index: macl.s
===================================================================
RCS file: macl.s
diff -N macl.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- macl.s 11 Aug 2003 19:34:00 -0000
***************
*** 0 ****
--- 1,54 ----
+ # sh testcase for mac.l
+ # mach: all
+ # as(sh): -defsym sim_cpu=0
+ # as(shdsp): -defsym sim_cpu=1 -dsp
+
+ .include "testutils.inc"
+
+ start
+ # force S-bit clear
+ clrs
+
+ init:
+ # Prime {MACL, MACH} to #1.
+ mov #1, r0
+ dmulu.l r0, r0
+
+ # Set up addresses.
+ mov.l pfour00, r0 ! 85
+ mov.l pfour12, r1 ! 17
+
+ test:
+ mac.l @r0+, @r1+
+
+ check:
+ # Check result.
+ assert_sreg 0, mach
+ assert_sreg 85*17+1, macl
+
+ # Ensure post-increment occurred.
+ assertreg0 four00+4
+ assertreg four12+4, r1
+
+ doubleinc:
+ mov.l pfour00, r0
+ mac.l @r0+, @r0+
+ assertreg0 four00+8
+
+
+ pass
+ exit 0
+
+ .align 1
+ four00:
+ .long 85
+ .long 2
+ four12:
+ .long 17
+ .long 3
+
+ .align 2
+ pfour00:
+ .long four00
+ pfour12:
+ .long four12
Index: macw.s
===================================================================
RCS file: macw.s
diff -N macw.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- macw.s 11 Aug 2003 19:34:00 -0000
***************
*** 0 ****
--- 1,56 ----
+ # sh testcase for mac.w
+ # mach: all
+ # as(sh): -defsym sim_cpu=0
+ # as(shdsp): -defsym sim_cpu=1 -dsp
+
+ .include "testutils.inc"
+
+ start
+ set_grs_a5a5
+
+ # Prime {MACL, MACH} to #1.
+ mov #1, r0
+ dmulu.l r0, r0
+
+ # Set up addresses.
+ mov.l pfour00, r0 ! 85
+ mov.l pfour12, r1 ! 17
+
+ test:
+ mac.w @r0+, @r1+ ! MAC = 85 * 17 + 1
+
+ check:
+ # Check result.
+ assert_sreg 0, mach
+ assert_sreg 85*17+1, macl
+
+ # Ensure post-increment occurred.
+ assertreg0 four00+2
+ assertreg four12+2, r1
+
+ doubleinc:
+ mov.l pfour00, r0
+ mac.w @r0+, @r0+
+ assertreg0 four00+4
+
+ set_greg 0xa5a5a5a5, r0
+ set_greg 0xa5a5a5a5, r1
+
+ test_grs_a5a5
+
+ pass
+ exit 0
+
+ .align 2
+ four00:
+ .word 85
+ .word 2
+ four12:
+ .word 17
+ .word 3
+
+
+ pfour00:
+ .long four00
+ pfour12:
+ .long four12