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On Mon, Jul 28, 2003 at 12:38:57PM -0400, Daniel Jacobowitz wrote:
On Mon, Jul 28, 2003 at 11:37:12AM -0400, Andrew Cagney wrote:
> I've checked this tweak into 6.0 and mainline:
>
> >2003-07-27 Andrew Cagney <cagney@redhat.com> > > > > * mips-tdep.c (print_gp_register_row): Print the GPR's register > > MOD NUM_REGS. > >
> > and this change into just the mainline (6.0 will follow in a few days if > no one notices a problem):
>
> >2003-07-27 Andrew Cagney <cagney@redhat.com> > > > > * regcache.c (struct regcache_descr): Update comments on > > nr_raw_registers. > > (init_legacy_regcache_descr): Don't set nr_raw_registers or > > sizeof_raw_register_valid_p. > > (init_regcache_descr): Set nr_raw_registers and > > sizeof_raw_register_valid_p before calling > > init_legacy_regcache_descr. > >
On a related note, before this change (2003-07-07 actually) mipsel-linux was completely broken. Info registers, in addition to printing R90, also claimed that all registers were zero. Backtraces broke for the same reason.
I haven't tried newer mainline yet; I will today or tomorrow.
Sorry, Andrew - we're almost there but MIPS register handling is still messed up. Take a look at "info all-registers":
(gdb) i all-registers zero at v0 v1 a0 a1 a2 a3 R0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 t0 t1 t2 t3 t4 t5 t6 t7 R8 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 s0 s1 s2 s3 s4 s5 s6 s7 R16 7fff7eaf 7fff7dcc 7fff7dd4 00000003 004059cc 10012808 00000000 00000000 t8 t9 k0 k1 gp sp s8 ra R24 00000000 00000000 00000000 00000000 00000000 7fff7df0 00000000 00000000 zero at v0 v1 a0 a1 00000000 0067194b 00000004 80279720 00000020 2aac0ac0 a2: 0xffffffff flt: nan dbl: nan a3: 0xffffffff flt: nan t0: 0xffffffff flt: nan dbl: nan t1: 0xffffffff flt: nan t2: 0xffffffff flt: nan dbl: nan t3: 0xffffffff flt: nan
Obviously the registers aren't where it expects them to be.
-- Daniel Jacobowitz MontaVista Software Debian GNU/Linux Developer
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