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[patch] Modelling fixes for fr500
- From: Dave Brolley <brolley at redhat dot com>
- To: gdb-patches at sources dot redhat dot com
- Date: Wed, 24 Sep 2003 15:10:09 -0400
- Subject: [patch] Modelling fixes for fr500
- Organization: Red Hat Canada, Ltd
I've committed the attached patch fixes some problems with insn
modelling for fr500:
1) commit insns were not being modelled
2) the ACC40Sk operand of mwtacc was not being passed to the modelling
functions.
3) Latency of SPR registers was not being tracked
4) Latency of ACC registers was not being tracked in some cases
This patch corrects these problems.
Daved
2003-09-24 Dave Brolley <brolley@redhat.com>
* frv.cpu (u-commit): New modelling unit for fr500.
(mwtaccg): Use frv_ref_SI to reference ACC40Sk as an input operand.
(commit-r): Use u-commit model for fr500.
(commit): Ditto.
(conditional-float-binary-op): Take profiling data as an argument.
Update callers.
(ne-float-binary-op): Ditto.
2003-09-24 Dave Brolley <brolley@redhat.com>
* profile.h (update_FR_ptime): New prototype.
(update_FRdouble_ptime): Ditto.
(update_SPR_ptime): Ditto.
(increase_ACC_busy): Ditto.
(enforce_full_acc_latency): Ditto.
(post_wait_for_SPR): Ditto.
* profile.c (update_FR_ptime): Moved here from profile-fr500.c.
(update_FRdouble_ptime): Ditto.
(update_SPR_ptime): New function.
(increase_ACC_busy): Ditto.
(enforce_full_acc_latency): Ditto.
(vliw_wait_for_fdiv_resource): Correct resource name.
(vliw_wait_for_fsqrt_resource): Ditto.
(post_wait_for_SPR): New function.
* profile-fr500.c (frvbf_model_fr500_u_commit): New function.
(frvbf_model_fr500_u_gr2fr): Pass out_FRk as output register to
adjust_float_register_busy.
(frvbf_model_fr500_u_gr_load): Record latency of SPR registers.
(frvbf_model_fr500_u_fr_load): Wait for and record latency of SPR
registers.
(frvbf_model_fr500_u_float_arith): Ditto.
(frvbf_model_fr500_u_float_dual_arith): Ditto.
(frvbf_model_fr500_u_float_div): Ditto.
(frvbf_model_fr500_u_float_sqrt): Ditto.
(frvbf_model_fr500_u_float_convert): Ditto.
(update_FR_ptime): Moved to profile.c
(update_FRdouble_ptime): Moved to profile.c
* profile-fr400.c (update_FR_ptime): Removed. Identical to functions
for other machines.
(update_FRdouble_ptime): Ditto.
* arch.h,cpu.h,sem.c,decode.[ch],model.c,sem.c: Regenerated.
Index: cpu/frv.cpu
===================================================================
RCS file: /cvs/src/src/cpu/frv.cpu,v
retrieving revision 1.12
diff -c -p -r1.12 frv.cpu
*** cpu/frv.cpu 19 Sep 2003 18:59:13 -0000 1.12
--- cpu/frv.cpu 24 Sep 2003 18:51:54 -0000
***************
*** 505,510 ****
--- 505,518 ----
() ; outputs
() ; profile action (default)
)
+ ; commit unit
+ (unit u-commit "Commit Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((GRk INT -1) (FRk INT -1)) ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
)
; Tomcat machine. Early version of fr500 machine
***************
*** 5798,5804 ****
(.str name "$pack $" reg "k")
(+ pack (.sym reg k) op (rs-null) ope (GRj-null))
(commit-semantics (index-of (.sym reg k)) is_float)
! ()
)
)
--- 5806,5812 ----
(.str name "$pack $" reg "k")
(+ pack (.sym reg k) op (rs-null) ope (GRj-null))
(commit-semantics (index-of (.sym reg k)) is_float)
! ((fr500 (unit u-commit)))
)
)
***************
*** 5812,5818 ****
(.str name "$pack")
(+ pack (rd-null) op (rs-null) ope (GRj-null))
(commit-semantics -1 is_float)
! ()
)
)
--- 5820,5826 ----
(.str name "$pack")
(+ pack (rd-null) op (rs-null) ope (GRj-null))
(commit-semantics -1 is_float)
! ((fr500 (unit u-commit)))
)
)
***************
*** 6118,6124 ****
(float-binary-op-d fmuld mul OP_7A OPE1_08 F-3 "mul double float")
(float-binary-op-d fdivd div OP_7A OPE1_09 F-4 "div double float")
! (define-pmacro (conditional-float-binary-op name pipe attr operation op ope comment)
(dni name
(comment)
(.splice (UNIT pipe) (MACH simple,tomcat,fr500,frv)
--- 6126,6132 ----
(float-binary-op-d fmuld mul OP_7A OPE1_08 F-3 "mul double float")
(float-binary-op-d fdivd div OP_7A OPE1_09 F-4 "div double float")
! (define-pmacro (conditional-float-binary-op name pipe attr operation op ope profile comment)
(dni name
(comment)
(.splice (UNIT pipe) (MACH simple,tomcat,fr500,frv)
***************
*** 6127,6142 ****
(+ pack FRk op FRi CCi cond ope FRj)
(if (eq CCi (or cond 2))
(set FRk (operation FRi FRj)))
! ((fr500 (unit u-float-arith)))
)
)
! (conditional-float-binary-op cfadds FMALL ((FR500-MAJOR F-2)) add OP_6D OPE4_0 "cond add single")
! (conditional-float-binary-op cfsubs FMALL ((FR500-MAJOR F-2)) sub OP_6D OPE4_1 "cond sub single")
! (conditional-float-binary-op cfmuls FM01 ((FR500-MAJOR F-3)) mul OP_6E OPE4_0 "cond mul single")
! (conditional-float-binary-op cfdivs FM01 ((FR500-MAJOR F-4)) div OP_6E OPE4_1 "cond div single")
! (define-pmacro (ne-float-binary-op name pipe attr operation op ope comment)
(dni name
(comment)
(.splice (UNIT pipe) (MACH simple,tomcat,fr500,frv)
--- 6135,6158 ----
(+ pack FRk op FRi CCi cond ope FRj)
(if (eq CCi (or cond 2))
(set FRk (operation FRi FRj)))
! profile
)
)
! (conditional-float-binary-op cfadds FMALL ((FR500-MAJOR F-2)) add OP_6D OPE4_0
! ((fr500 (unit u-float-arith)))
! "cond add single")
! (conditional-float-binary-op cfsubs FMALL ((FR500-MAJOR F-2)) sub OP_6D OPE4_1
! ((fr500 (unit u-float-arith)))
! "cond sub single")
! (conditional-float-binary-op cfmuls FM01 ((FR500-MAJOR F-3)) mul OP_6E OPE4_0
! ((fr500 (unit u-float-arith)))
! "cond mul single")
! (conditional-float-binary-op cfdivs FM01 ((FR500-MAJOR F-4)) div OP_6E OPE4_1
! ((fr500 (unit u-float-div)))
! "cond div single")
! (define-pmacro (ne-float-binary-op name pipe attr operation op ope profile comment)
(dni name
(comment)
(.splice (UNIT pipe) (MACH simple,tomcat,fr500,frv)
***************
*** 6146,6159 ****
(sequence ()
(c-call VOID "@cpu@_set_ne_index" (index-of FRk))
(set FRk (operation FRi FRj)))
! ((fr500 (unit u-float-arith)))
)
)
! (ne-float-binary-op nfadds FMALL ((FR500-MAJOR F-2)) add OP_79 OPE1_26 "ne add single")
! (ne-float-binary-op nfsubs FMALL ((FR500-MAJOR F-2)) sub OP_79 OPE1_27 "ne sub single")
! (ne-float-binary-op nfmuls FM01 ((FR500-MAJOR F-3)) mul OP_79 OPE1_28 "ne mul single")
! (ne-float-binary-op nfdivs FM01 ((FR500-MAJOR F-4)) div OP_79 OPE1_29 "ne div single")
(define-pmacro (fcc-eq) 8)
(define-pmacro (fcc-lt) 4)
--- 6162,6183 ----
(sequence ()
(c-call VOID "@cpu@_set_ne_index" (index-of FRk))
(set FRk (operation FRi FRj)))
! profile
)
)
! (ne-float-binary-op nfadds FMALL ((FR500-MAJOR F-2)) add OP_79 OPE1_26
! ((fr500 (unit u-float-arith)))
! "ne add single")
! (ne-float-binary-op nfsubs FMALL ((FR500-MAJOR F-2)) sub OP_79 OPE1_27
! ((fr500 (unit u-float-arith)))
! "ne sub single")
! (ne-float-binary-op nfmuls FM01 ((FR500-MAJOR F-3)) mul OP_79 OPE1_28
! ((fr500 (unit u-float-arith)))
! "ne mul single")
! (ne-float-binary-op nfdivs FM01 ((FR500-MAJOR F-4)) div OP_79 OPE1_29
! ((fr500 (unit u-float-div)))
! "ne div single")
(define-pmacro (fcc-eq) 8)
(define-pmacro (fcc-lt) 4)
***************
*** 8193,8199 ****
((UNIT FM01) (FR500-MAJOR M-3) (FR400-MAJOR M-1))
"mwtaccg$pack $FRinti,$ACCGk"
(+ pack ACCGk OP_7B FRinti OPE1_3F (FRj-null))
! (set ACCGk FRinti)
((fr400 (unit u-media-4-accg))
(fr500 (unit u-media)))
)
--- 8217,8226 ----
((UNIT FM01) (FR500-MAJOR M-3) (FR400-MAJOR M-1))
"mwtaccg$pack $FRinti,$ACCGk"
(+ pack ACCGk OP_7B FRinti OPE1_3F (FRj-null))
! (sequence ()
! ; hack to get these referenced for profiling
! (c-raw-call VOID "frv_ref_SI" ACCGk)
! (set ACCGk FRinti))
((fr400 (unit u-media-4-accg))
(fr500 (unit u-media)))
)
Index: opcodes/frv-desc.c
===================================================================
RCS file: /cvs/src/src/opcodes/frv-desc.c,v
retrieving revision 1.8
diff -c -p -r1.8 frv-desc.c
*** opcodes/frv-desc.c 9 Sep 2003 22:29:42 -0000 1.8
--- opcodes/frv-desc.c 24 Sep 2003 18:52:15 -0000
*************** static const CGEN_IBASE frv_cgen_insn_ta
*** 3091,3101 ****
FRV_INSN_LDQFI, "ldqfi", "ldqfi", 32,
{ 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
},
- /* nldqi$pack @($GRi,$d12),$GRk */
- {
- FRV_INSN_NLDQI, "nldqi", "nldqi", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } }
- },
/* nldqfi$pack @($GRi,$d12),$FRintk */
{
FRV_INSN_NLDQFI, "nldqfi", "nldqfi", 32,
--- 3091,3096 ----
Index: opcodes/frv-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/frv-opc.c,v
retrieving revision 1.5
diff -c -p -r1.5 frv-opc.c
*** opcodes/frv-opc.c 3 Sep 2003 23:09:56 -0000 1.5
--- opcodes/frv-opc.c 24 Sep 2003 18:52:15 -0000
*************** static const CGEN_OPCODE frv_cgen_insn_o
*** 2177,2188 ****
{ { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } },
& ifmt_ldbfi, { 0xf00000 }
},
- /* nldqi$pack @($GRi,$d12),$GRk */
- {
- { 0, 0, 0, 0 },
- { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } },
- & ifmt_ldsbi, { 0x1180000 }
- },
/* nldqfi$pack @($GRi,$d12),$FRintk */
{
{ 0, 0, 0, 0 },
--- 2177,2182 ----
Index: opcodes/frv-opc.h
===================================================================
RCS file: /cvs/src/src/opcodes/frv-opc.h,v
retrieving revision 1.4
diff -c -p -r1.4 frv-opc.h
*** opcodes/frv-opc.h 3 Sep 2003 23:09:56 -0000 1.4
--- opcodes/frv-opc.h 24 Sep 2003 18:52:15 -0000
*************** typedef enum cgen_insn_type {
*** 102,253 ****
, FRV_INSN_LDFI, FRV_INSN_NLDSBI, FRV_INSN_NLDUBI, FRV_INSN_NLDSHI
, FRV_INSN_NLDUHI, FRV_INSN_NLDI, FRV_INSN_NLDBFI, FRV_INSN_NLDHFI
, FRV_INSN_NLDFI, FRV_INSN_LDDI, FRV_INSN_LDDFI, FRV_INSN_NLDDI
! , FRV_INSN_NLDDFI, FRV_INSN_LDQI, FRV_INSN_LDQFI, FRV_INSN_NLDQI
! , FRV_INSN_NLDQFI, FRV_INSN_STB, FRV_INSN_STH, FRV_INSN_ST
! , FRV_INSN_STBF, FRV_INSN_STHF, FRV_INSN_STF, FRV_INSN_STC
! , FRV_INSN_RSTB, FRV_INSN_RSTH, FRV_INSN_RST, FRV_INSN_RSTBF
! , FRV_INSN_RSTHF, FRV_INSN_RSTF, FRV_INSN_STD, FRV_INSN_STDF
! , FRV_INSN_STDC, FRV_INSN_RSTD, FRV_INSN_RSTDF, FRV_INSN_STQ
! , FRV_INSN_STQF, FRV_INSN_STQC, FRV_INSN_RSTQ, FRV_INSN_RSTQF
! , FRV_INSN_STBU, FRV_INSN_STHU, FRV_INSN_STU, FRV_INSN_STBFU
! , FRV_INSN_STHFU, FRV_INSN_STFU, FRV_INSN_STCU, FRV_INSN_STDU
! , FRV_INSN_STDFU, FRV_INSN_STDCU, FRV_INSN_STQU, FRV_INSN_STQFU
! , FRV_INSN_STQCU, FRV_INSN_CLDSB, FRV_INSN_CLDUB, FRV_INSN_CLDSH
! , FRV_INSN_CLDUH, FRV_INSN_CLD, FRV_INSN_CLDBF, FRV_INSN_CLDHF
! , FRV_INSN_CLDF, FRV_INSN_CLDD, FRV_INSN_CLDDF, FRV_INSN_CLDQ
! , FRV_INSN_CLDSBU, FRV_INSN_CLDUBU, FRV_INSN_CLDSHU, FRV_INSN_CLDUHU
! , FRV_INSN_CLDU, FRV_INSN_CLDBFU, FRV_INSN_CLDHFU, FRV_INSN_CLDFU
! , FRV_INSN_CLDDU, FRV_INSN_CLDDFU, FRV_INSN_CLDQU, FRV_INSN_CSTB
! , FRV_INSN_CSTH, FRV_INSN_CST, FRV_INSN_CSTBF, FRV_INSN_CSTHF
! , FRV_INSN_CSTF, FRV_INSN_CSTD, FRV_INSN_CSTDF, FRV_INSN_CSTQ
! , FRV_INSN_CSTBU, FRV_INSN_CSTHU, FRV_INSN_CSTU, FRV_INSN_CSTBFU
! , FRV_INSN_CSTHFU, FRV_INSN_CSTFU, FRV_INSN_CSTDU, FRV_INSN_CSTDFU
! , FRV_INSN_STBI, FRV_INSN_STHI, FRV_INSN_STI, FRV_INSN_STBFI
! , FRV_INSN_STHFI, FRV_INSN_STFI, FRV_INSN_STDI, FRV_INSN_STDFI
! , FRV_INSN_STQI, FRV_INSN_STQFI, FRV_INSN_SWAP, FRV_INSN_SWAPI
! , FRV_INSN_CSWAP, FRV_INSN_MOVGF, FRV_INSN_MOVFG, FRV_INSN_MOVGFD
! , FRV_INSN_MOVFGD, FRV_INSN_MOVGFQ, FRV_INSN_MOVFGQ, FRV_INSN_CMOVGF
! , FRV_INSN_CMOVFG, FRV_INSN_CMOVGFD, FRV_INSN_CMOVFGD, FRV_INSN_MOVGS
! , FRV_INSN_MOVSG, FRV_INSN_BRA, FRV_INSN_BNO, FRV_INSN_BEQ
! , FRV_INSN_BNE, FRV_INSN_BLE, FRV_INSN_BGT, FRV_INSN_BLT
! , FRV_INSN_BGE, FRV_INSN_BLS, FRV_INSN_BHI, FRV_INSN_BC
! , FRV_INSN_BNC, FRV_INSN_BN, FRV_INSN_BP, FRV_INSN_BV
! , FRV_INSN_BNV, FRV_INSN_FBRA, FRV_INSN_FBNO, FRV_INSN_FBNE
! , FRV_INSN_FBEQ, FRV_INSN_FBLG, FRV_INSN_FBUE, FRV_INSN_FBUL
! , FRV_INSN_FBGE, FRV_INSN_FBLT, FRV_INSN_FBUGE, FRV_INSN_FBUG
! , FRV_INSN_FBLE, FRV_INSN_FBGT, FRV_INSN_FBULE, FRV_INSN_FBU
! , FRV_INSN_FBO, FRV_INSN_BCTRLR, FRV_INSN_BRALR, FRV_INSN_BNOLR
! , FRV_INSN_BEQLR, FRV_INSN_BNELR, FRV_INSN_BLELR, FRV_INSN_BGTLR
! , FRV_INSN_BLTLR, FRV_INSN_BGELR, FRV_INSN_BLSLR, FRV_INSN_BHILR
! , FRV_INSN_BCLR, FRV_INSN_BNCLR, FRV_INSN_BNLR, FRV_INSN_BPLR
! , FRV_INSN_BVLR, FRV_INSN_BNVLR, FRV_INSN_FBRALR, FRV_INSN_FBNOLR
! , FRV_INSN_FBEQLR, FRV_INSN_FBNELR, FRV_INSN_FBLGLR, FRV_INSN_FBUELR
! , FRV_INSN_FBULLR, FRV_INSN_FBGELR, FRV_INSN_FBLTLR, FRV_INSN_FBUGELR
! , FRV_INSN_FBUGLR, FRV_INSN_FBLELR, FRV_INSN_FBGTLR, FRV_INSN_FBULELR
! , FRV_INSN_FBULR, FRV_INSN_FBOLR, FRV_INSN_BCRALR, FRV_INSN_BCNOLR
! , FRV_INSN_BCEQLR, FRV_INSN_BCNELR, FRV_INSN_BCLELR, FRV_INSN_BCGTLR
! , FRV_INSN_BCLTLR, FRV_INSN_BCGELR, FRV_INSN_BCLSLR, FRV_INSN_BCHILR
! , FRV_INSN_BCCLR, FRV_INSN_BCNCLR, FRV_INSN_BCNLR, FRV_INSN_BCPLR
! , FRV_INSN_BCVLR, FRV_INSN_BCNVLR, FRV_INSN_FCBRALR, FRV_INSN_FCBNOLR
! , FRV_INSN_FCBEQLR, FRV_INSN_FCBNELR, FRV_INSN_FCBLGLR, FRV_INSN_FCBUELR
! , FRV_INSN_FCBULLR, FRV_INSN_FCBGELR, FRV_INSN_FCBLTLR, FRV_INSN_FCBUGELR
! , FRV_INSN_FCBUGLR, FRV_INSN_FCBLELR, FRV_INSN_FCBGTLR, FRV_INSN_FCBULELR
! , FRV_INSN_FCBULR, FRV_INSN_FCBOLR, FRV_INSN_JMPL, FRV_INSN_CALLL
! , FRV_INSN_JMPIL, FRV_INSN_CALLIL, FRV_INSN_CALL, FRV_INSN_RETT
! , FRV_INSN_REI, FRV_INSN_TRA, FRV_INSN_TNO, FRV_INSN_TEQ
! , FRV_INSN_TNE, FRV_INSN_TLE, FRV_INSN_TGT, FRV_INSN_TLT
! , FRV_INSN_TGE, FRV_INSN_TLS, FRV_INSN_THI, FRV_INSN_TC
! , FRV_INSN_TNC, FRV_INSN_TN, FRV_INSN_TP, FRV_INSN_TV
! , FRV_INSN_TNV, FRV_INSN_FTRA, FRV_INSN_FTNO, FRV_INSN_FTNE
! , FRV_INSN_FTEQ, FRV_INSN_FTLG, FRV_INSN_FTUE, FRV_INSN_FTUL
! , FRV_INSN_FTGE, FRV_INSN_FTLT, FRV_INSN_FTUGE, FRV_INSN_FTUG
! , FRV_INSN_FTLE, FRV_INSN_FTGT, FRV_INSN_FTULE, FRV_INSN_FTU
! , FRV_INSN_FTO, FRV_INSN_TIRA, FRV_INSN_TINO, FRV_INSN_TIEQ
! , FRV_INSN_TINE, FRV_INSN_TILE, FRV_INSN_TIGT, FRV_INSN_TILT
! , FRV_INSN_TIGE, FRV_INSN_TILS, FRV_INSN_TIHI, FRV_INSN_TIC
! , FRV_INSN_TINC, FRV_INSN_TIN, FRV_INSN_TIP, FRV_INSN_TIV
! , FRV_INSN_TINV, FRV_INSN_FTIRA, FRV_INSN_FTINO, FRV_INSN_FTINE
! , FRV_INSN_FTIEQ, FRV_INSN_FTILG, FRV_INSN_FTIUE, FRV_INSN_FTIUL
! , FRV_INSN_FTIGE, FRV_INSN_FTILT, FRV_INSN_FTIUGE, FRV_INSN_FTIUG
! , FRV_INSN_FTILE, FRV_INSN_FTIGT, FRV_INSN_FTIULE, FRV_INSN_FTIU
! , FRV_INSN_FTIO, FRV_INSN_BREAK, FRV_INSN_MTRAP, FRV_INSN_ANDCR
! , FRV_INSN_ORCR, FRV_INSN_XORCR, FRV_INSN_NANDCR, FRV_INSN_NORCR
! , FRV_INSN_ANDNCR, FRV_INSN_ORNCR, FRV_INSN_NANDNCR, FRV_INSN_NORNCR
! , FRV_INSN_NOTCR, FRV_INSN_CKRA, FRV_INSN_CKNO, FRV_INSN_CKEQ
! , FRV_INSN_CKNE, FRV_INSN_CKLE, FRV_INSN_CKGT, FRV_INSN_CKLT
! , FRV_INSN_CKGE, FRV_INSN_CKLS, FRV_INSN_CKHI, FRV_INSN_CKC
! , FRV_INSN_CKNC, FRV_INSN_CKN, FRV_INSN_CKP, FRV_INSN_CKV
! , FRV_INSN_CKNV, FRV_INSN_FCKRA, FRV_INSN_FCKNO, FRV_INSN_FCKNE
! , FRV_INSN_FCKEQ, FRV_INSN_FCKLG, FRV_INSN_FCKUE, FRV_INSN_FCKUL
! , FRV_INSN_FCKGE, FRV_INSN_FCKLT, FRV_INSN_FCKUGE, FRV_INSN_FCKUG
! , FRV_INSN_FCKLE, FRV_INSN_FCKGT, FRV_INSN_FCKULE, FRV_INSN_FCKU
! , FRV_INSN_FCKO, FRV_INSN_CCKRA, FRV_INSN_CCKNO, FRV_INSN_CCKEQ
! , FRV_INSN_CCKNE, FRV_INSN_CCKLE, FRV_INSN_CCKGT, FRV_INSN_CCKLT
! , FRV_INSN_CCKGE, FRV_INSN_CCKLS, FRV_INSN_CCKHI, FRV_INSN_CCKC
! , FRV_INSN_CCKNC, FRV_INSN_CCKN, FRV_INSN_CCKP, FRV_INSN_CCKV
! , FRV_INSN_CCKNV, FRV_INSN_CFCKRA, FRV_INSN_CFCKNO, FRV_INSN_CFCKNE
! , FRV_INSN_CFCKEQ, FRV_INSN_CFCKLG, FRV_INSN_CFCKUE, FRV_INSN_CFCKUL
! , FRV_INSN_CFCKGE, FRV_INSN_CFCKLT, FRV_INSN_CFCKUGE, FRV_INSN_CFCKUG
! , FRV_INSN_CFCKLE, FRV_INSN_CFCKGT, FRV_INSN_CFCKULE, FRV_INSN_CFCKU
! , FRV_INSN_CFCKO, FRV_INSN_CJMPL, FRV_INSN_CCALLL, FRV_INSN_ICI
! , FRV_INSN_DCI, FRV_INSN_ICEI, FRV_INSN_DCEI, FRV_INSN_DCF
! , FRV_INSN_DCEF, FRV_INSN_WITLB, FRV_INSN_WDTLB, FRV_INSN_ITLBI
! , FRV_INSN_DTLBI, FRV_INSN_ICPL, FRV_INSN_DCPL, FRV_INSN_ICUL
! , FRV_INSN_DCUL, FRV_INSN_BAR, FRV_INSN_MEMBAR, FRV_INSN_COP1
! , FRV_INSN_COP2, FRV_INSN_CLRGR, FRV_INSN_CLRFR, FRV_INSN_CLRGA
! , FRV_INSN_CLRFA, FRV_INSN_COMMITGR, FRV_INSN_COMMITFR, FRV_INSN_COMMITGA
! , FRV_INSN_COMMITFA, FRV_INSN_FITOS, FRV_INSN_FSTOI, FRV_INSN_FITOD
! , FRV_INSN_FDTOI, FRV_INSN_FDITOS, FRV_INSN_FDSTOI, FRV_INSN_NFDITOS
! , FRV_INSN_NFDSTOI, FRV_INSN_CFITOS, FRV_INSN_CFSTOI, FRV_INSN_NFITOS
! , FRV_INSN_NFSTOI, FRV_INSN_FMOVS, FRV_INSN_FMOVD, FRV_INSN_FDMOVS
! , FRV_INSN_CFMOVS, FRV_INSN_FNEGS, FRV_INSN_FNEGD, FRV_INSN_FDNEGS
! , FRV_INSN_CFNEGS, FRV_INSN_FABSS, FRV_INSN_FABSD, FRV_INSN_FDABSS
! , FRV_INSN_CFABSS, FRV_INSN_FSQRTS, FRV_INSN_FDSQRTS, FRV_INSN_NFDSQRTS
! , FRV_INSN_FSQRTD, FRV_INSN_CFSQRTS, FRV_INSN_NFSQRTS, FRV_INSN_FADDS
! , FRV_INSN_FSUBS, FRV_INSN_FMULS, FRV_INSN_FDIVS, FRV_INSN_FADDD
! , FRV_INSN_FSUBD, FRV_INSN_FMULD, FRV_INSN_FDIVD, FRV_INSN_CFADDS
! , FRV_INSN_CFSUBS, FRV_INSN_CFMULS, FRV_INSN_CFDIVS, FRV_INSN_NFADDS
! , FRV_INSN_NFSUBS, FRV_INSN_NFMULS, FRV_INSN_NFDIVS, FRV_INSN_FCMPS
! , FRV_INSN_FCMPD, FRV_INSN_CFCMPS, FRV_INSN_FDCMPS, FRV_INSN_FMADDS
! , FRV_INSN_FMSUBS, FRV_INSN_FMADDD, FRV_INSN_FMSUBD, FRV_INSN_FDMADDS
! , FRV_INSN_NFDMADDS, FRV_INSN_CFMADDS, FRV_INSN_CFMSUBS, FRV_INSN_NFMADDS
! , FRV_INSN_NFMSUBS, FRV_INSN_FMAS, FRV_INSN_FMSS, FRV_INSN_FDMAS
! , FRV_INSN_FDMSS, FRV_INSN_NFDMAS, FRV_INSN_NFDMSS, FRV_INSN_CFMAS
! , FRV_INSN_CFMSS, FRV_INSN_FMAD, FRV_INSN_FMSD, FRV_INSN_NFMAS
! , FRV_INSN_NFMSS, FRV_INSN_FDADDS, FRV_INSN_FDSUBS, FRV_INSN_FDMULS
! , FRV_INSN_FDDIVS, FRV_INSN_FDSADS, FRV_INSN_FDMULCS, FRV_INSN_NFDMULCS
! , FRV_INSN_NFDADDS, FRV_INSN_NFDSUBS, FRV_INSN_NFDMULS, FRV_INSN_NFDDIVS
! , FRV_INSN_NFDSADS, FRV_INSN_NFDCMPS, FRV_INSN_MHSETLOS, FRV_INSN_MHSETHIS
! , FRV_INSN_MHDSETS, FRV_INSN_MHSETLOH, FRV_INSN_MHSETHIH, FRV_INSN_MHDSETH
! , FRV_INSN_MAND, FRV_INSN_MOR, FRV_INSN_MXOR, FRV_INSN_CMAND
! , FRV_INSN_CMOR, FRV_INSN_CMXOR, FRV_INSN_MNOT, FRV_INSN_CMNOT
! , FRV_INSN_MROTLI, FRV_INSN_MROTRI, FRV_INSN_MWCUT, FRV_INSN_MWCUTI
! , FRV_INSN_MCUT, FRV_INSN_MCUTI, FRV_INSN_MCUTSS, FRV_INSN_MCUTSSI
! , FRV_INSN_MDCUTSSI, FRV_INSN_MAVEH, FRV_INSN_MSLLHI, FRV_INSN_MSRLHI
! , FRV_INSN_MSRAHI, FRV_INSN_MDROTLI, FRV_INSN_MCPLHI, FRV_INSN_MCPLI
! , FRV_INSN_MSATHS, FRV_INSN_MQSATHS, FRV_INSN_MSATHU, FRV_INSN_MCMPSH
! , FRV_INSN_MCMPUH, FRV_INSN_MABSHS, FRV_INSN_MADDHSS, FRV_INSN_MADDHUS
! , FRV_INSN_MSUBHSS, FRV_INSN_MSUBHUS, FRV_INSN_CMADDHSS, FRV_INSN_CMADDHUS
! , FRV_INSN_CMSUBHSS, FRV_INSN_CMSUBHUS, FRV_INSN_MQADDHSS, FRV_INSN_MQADDHUS
! , FRV_INSN_MQSUBHSS, FRV_INSN_MQSUBHUS, FRV_INSN_CMQADDHSS, FRV_INSN_CMQADDHUS
! , FRV_INSN_CMQSUBHSS, FRV_INSN_CMQSUBHUS, FRV_INSN_MADDACCS, FRV_INSN_MSUBACCS
! , FRV_INSN_MDADDACCS, FRV_INSN_MDSUBACCS, FRV_INSN_MASACCS, FRV_INSN_MDASACCS
! , FRV_INSN_MMULHS, FRV_INSN_MMULHU, FRV_INSN_MMULXHS, FRV_INSN_MMULXHU
! , FRV_INSN_CMMULHS, FRV_INSN_CMMULHU, FRV_INSN_MQMULHS, FRV_INSN_MQMULHU
! , FRV_INSN_MQMULXHS, FRV_INSN_MQMULXHU, FRV_INSN_CMQMULHS, FRV_INSN_CMQMULHU
! , FRV_INSN_MMACHS, FRV_INSN_MMACHU, FRV_INSN_MMRDHS, FRV_INSN_MMRDHU
! , FRV_INSN_CMMACHS, FRV_INSN_CMMACHU, FRV_INSN_MQMACHS, FRV_INSN_MQMACHU
! , FRV_INSN_CMQMACHS, FRV_INSN_CMQMACHU, FRV_INSN_MQXMACHS, FRV_INSN_MQXMACXHS
! , FRV_INSN_MQMACXHS, FRV_INSN_MCPXRS, FRV_INSN_MCPXRU, FRV_INSN_MCPXIS
! , FRV_INSN_MCPXIU, FRV_INSN_CMCPXRS, FRV_INSN_CMCPXRU, FRV_INSN_CMCPXIS
! , FRV_INSN_CMCPXIU, FRV_INSN_MQCPXRS, FRV_INSN_MQCPXRU, FRV_INSN_MQCPXIS
! , FRV_INSN_MQCPXIU, FRV_INSN_MEXPDHW, FRV_INSN_CMEXPDHW, FRV_INSN_MEXPDHD
! , FRV_INSN_CMEXPDHD, FRV_INSN_MPACKH, FRV_INSN_MDPACKH, FRV_INSN_MUNPACKH
! , FRV_INSN_MDUNPACKH, FRV_INSN_MBTOH, FRV_INSN_CMBTOH, FRV_INSN_MHTOB
! , FRV_INSN_CMHTOB, FRV_INSN_MBTOHE, FRV_INSN_CMBTOHE, FRV_INSN_MNOP
! , FRV_INSN_MCLRACC_0, FRV_INSN_MCLRACC_1, FRV_INSN_MRDACC, FRV_INSN_MRDACCG
! , FRV_INSN_MWTACC, FRV_INSN_MWTACCG, FRV_INSN_MCOP1, FRV_INSN_MCOP2
! , FRV_INSN_FNOP
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */
--- 102,252 ----
, FRV_INSN_LDFI, FRV_INSN_NLDSBI, FRV_INSN_NLDUBI, FRV_INSN_NLDSHI
, FRV_INSN_NLDUHI, FRV_INSN_NLDI, FRV_INSN_NLDBFI, FRV_INSN_NLDHFI
, FRV_INSN_NLDFI, FRV_INSN_LDDI, FRV_INSN_LDDFI, FRV_INSN_NLDDI
! , FRV_INSN_NLDDFI, FRV_INSN_LDQI, FRV_INSN_LDQFI, FRV_INSN_NLDQFI
! , FRV_INSN_STB, FRV_INSN_STH, FRV_INSN_ST, FRV_INSN_STBF
! , FRV_INSN_STHF, FRV_INSN_STF, FRV_INSN_STC, FRV_INSN_RSTB
! , FRV_INSN_RSTH, FRV_INSN_RST, FRV_INSN_RSTBF, FRV_INSN_RSTHF
! , FRV_INSN_RSTF, FRV_INSN_STD, FRV_INSN_STDF, FRV_INSN_STDC
! , FRV_INSN_RSTD, FRV_INSN_RSTDF, FRV_INSN_STQ, FRV_INSN_STQF
! , FRV_INSN_STQC, FRV_INSN_RSTQ, FRV_INSN_RSTQF, FRV_INSN_STBU
! , FRV_INSN_STHU, FRV_INSN_STU, FRV_INSN_STBFU, FRV_INSN_STHFU
! , FRV_INSN_STFU, FRV_INSN_STCU, FRV_INSN_STDU, FRV_INSN_STDFU
! , FRV_INSN_STDCU, FRV_INSN_STQU, FRV_INSN_STQFU, FRV_INSN_STQCU
! , FRV_INSN_CLDSB, FRV_INSN_CLDUB, FRV_INSN_CLDSH, FRV_INSN_CLDUH
! , FRV_INSN_CLD, FRV_INSN_CLDBF, FRV_INSN_CLDHF, FRV_INSN_CLDF
! , FRV_INSN_CLDD, FRV_INSN_CLDDF, FRV_INSN_CLDQ, FRV_INSN_CLDSBU
! , FRV_INSN_CLDUBU, FRV_INSN_CLDSHU, FRV_INSN_CLDUHU, FRV_INSN_CLDU
! , FRV_INSN_CLDBFU, FRV_INSN_CLDHFU, FRV_INSN_CLDFU, FRV_INSN_CLDDU
! , FRV_INSN_CLDDFU, FRV_INSN_CLDQU, FRV_INSN_CSTB, FRV_INSN_CSTH
! , FRV_INSN_CST, FRV_INSN_CSTBF, FRV_INSN_CSTHF, FRV_INSN_CSTF
! , FRV_INSN_CSTD, FRV_INSN_CSTDF, FRV_INSN_CSTQ, FRV_INSN_CSTBU
! , FRV_INSN_CSTHU, FRV_INSN_CSTU, FRV_INSN_CSTBFU, FRV_INSN_CSTHFU
! , FRV_INSN_CSTFU, FRV_INSN_CSTDU, FRV_INSN_CSTDFU, FRV_INSN_STBI
! , FRV_INSN_STHI, FRV_INSN_STI, FRV_INSN_STBFI, FRV_INSN_STHFI
! , FRV_INSN_STFI, FRV_INSN_STDI, FRV_INSN_STDFI, FRV_INSN_STQI
! , FRV_INSN_STQFI, FRV_INSN_SWAP, FRV_INSN_SWAPI, FRV_INSN_CSWAP
! , FRV_INSN_MOVGF, FRV_INSN_MOVFG, FRV_INSN_MOVGFD, FRV_INSN_MOVFGD
! , FRV_INSN_MOVGFQ, FRV_INSN_MOVFGQ, FRV_INSN_CMOVGF, FRV_INSN_CMOVFG
! , FRV_INSN_CMOVGFD, FRV_INSN_CMOVFGD, FRV_INSN_MOVGS, FRV_INSN_MOVSG
! , FRV_INSN_BRA, FRV_INSN_BNO, FRV_INSN_BEQ, FRV_INSN_BNE
! , FRV_INSN_BLE, FRV_INSN_BGT, FRV_INSN_BLT, FRV_INSN_BGE
! , FRV_INSN_BLS, FRV_INSN_BHI, FRV_INSN_BC, FRV_INSN_BNC
! , FRV_INSN_BN, FRV_INSN_BP, FRV_INSN_BV, FRV_INSN_BNV
! , FRV_INSN_FBRA, FRV_INSN_FBNO, FRV_INSN_FBNE, FRV_INSN_FBEQ
! , FRV_INSN_FBLG, FRV_INSN_FBUE, FRV_INSN_FBUL, FRV_INSN_FBGE
! , FRV_INSN_FBLT, FRV_INSN_FBUGE, FRV_INSN_FBUG, FRV_INSN_FBLE
! , FRV_INSN_FBGT, FRV_INSN_FBULE, FRV_INSN_FBU, FRV_INSN_FBO
! , FRV_INSN_BCTRLR, FRV_INSN_BRALR, FRV_INSN_BNOLR, FRV_INSN_BEQLR
! , FRV_INSN_BNELR, FRV_INSN_BLELR, FRV_INSN_BGTLR, FRV_INSN_BLTLR
! , FRV_INSN_BGELR, FRV_INSN_BLSLR, FRV_INSN_BHILR, FRV_INSN_BCLR
! , FRV_INSN_BNCLR, FRV_INSN_BNLR, FRV_INSN_BPLR, FRV_INSN_BVLR
! , FRV_INSN_BNVLR, FRV_INSN_FBRALR, FRV_INSN_FBNOLR, FRV_INSN_FBEQLR
! , FRV_INSN_FBNELR, FRV_INSN_FBLGLR, FRV_INSN_FBUELR, FRV_INSN_FBULLR
! , FRV_INSN_FBGELR, FRV_INSN_FBLTLR, FRV_INSN_FBUGELR, FRV_INSN_FBUGLR
! , FRV_INSN_FBLELR, FRV_INSN_FBGTLR, FRV_INSN_FBULELR, FRV_INSN_FBULR
! , FRV_INSN_FBOLR, FRV_INSN_BCRALR, FRV_INSN_BCNOLR, FRV_INSN_BCEQLR
! , FRV_INSN_BCNELR, FRV_INSN_BCLELR, FRV_INSN_BCGTLR, FRV_INSN_BCLTLR
! , FRV_INSN_BCGELR, FRV_INSN_BCLSLR, FRV_INSN_BCHILR, FRV_INSN_BCCLR
! , FRV_INSN_BCNCLR, FRV_INSN_BCNLR, FRV_INSN_BCPLR, FRV_INSN_BCVLR
! , FRV_INSN_BCNVLR, FRV_INSN_FCBRALR, FRV_INSN_FCBNOLR, FRV_INSN_FCBEQLR
! , FRV_INSN_FCBNELR, FRV_INSN_FCBLGLR, FRV_INSN_FCBUELR, FRV_INSN_FCBULLR
! , FRV_INSN_FCBGELR, FRV_INSN_FCBLTLR, FRV_INSN_FCBUGELR, FRV_INSN_FCBUGLR
! , FRV_INSN_FCBLELR, FRV_INSN_FCBGTLR, FRV_INSN_FCBULELR, FRV_INSN_FCBULR
! , FRV_INSN_FCBOLR, FRV_INSN_JMPL, FRV_INSN_CALLL, FRV_INSN_JMPIL
! , FRV_INSN_CALLIL, FRV_INSN_CALL, FRV_INSN_RETT, FRV_INSN_REI
! , FRV_INSN_TRA, FRV_INSN_TNO, FRV_INSN_TEQ, FRV_INSN_TNE
! , FRV_INSN_TLE, FRV_INSN_TGT, FRV_INSN_TLT, FRV_INSN_TGE
! , FRV_INSN_TLS, FRV_INSN_THI, FRV_INSN_TC, FRV_INSN_TNC
! , FRV_INSN_TN, FRV_INSN_TP, FRV_INSN_TV, FRV_INSN_TNV
! , FRV_INSN_FTRA, FRV_INSN_FTNO, FRV_INSN_FTNE, FRV_INSN_FTEQ
! , FRV_INSN_FTLG, FRV_INSN_FTUE, FRV_INSN_FTUL, FRV_INSN_FTGE
! , FRV_INSN_FTLT, FRV_INSN_FTUGE, FRV_INSN_FTUG, FRV_INSN_FTLE
! , FRV_INSN_FTGT, FRV_INSN_FTULE, FRV_INSN_FTU, FRV_INSN_FTO
! , FRV_INSN_TIRA, FRV_INSN_TINO, FRV_INSN_TIEQ, FRV_INSN_TINE
! , FRV_INSN_TILE, FRV_INSN_TIGT, FRV_INSN_TILT, FRV_INSN_TIGE
! , FRV_INSN_TILS, FRV_INSN_TIHI, FRV_INSN_TIC, FRV_INSN_TINC
! , FRV_INSN_TIN, FRV_INSN_TIP, FRV_INSN_TIV, FRV_INSN_TINV
! , FRV_INSN_FTIRA, FRV_INSN_FTINO, FRV_INSN_FTINE, FRV_INSN_FTIEQ
! , FRV_INSN_FTILG, FRV_INSN_FTIUE, FRV_INSN_FTIUL, FRV_INSN_FTIGE
! , FRV_INSN_FTILT, FRV_INSN_FTIUGE, FRV_INSN_FTIUG, FRV_INSN_FTILE
! , FRV_INSN_FTIGT, FRV_INSN_FTIULE, FRV_INSN_FTIU, FRV_INSN_FTIO
! , FRV_INSN_BREAK, FRV_INSN_MTRAP, FRV_INSN_ANDCR, FRV_INSN_ORCR
! , FRV_INSN_XORCR, FRV_INSN_NANDCR, FRV_INSN_NORCR, FRV_INSN_ANDNCR
! , FRV_INSN_ORNCR, FRV_INSN_NANDNCR, FRV_INSN_NORNCR, FRV_INSN_NOTCR
! , FRV_INSN_CKRA, FRV_INSN_CKNO, FRV_INSN_CKEQ, FRV_INSN_CKNE
! , FRV_INSN_CKLE, FRV_INSN_CKGT, FRV_INSN_CKLT, FRV_INSN_CKGE
! , FRV_INSN_CKLS, FRV_INSN_CKHI, FRV_INSN_CKC, FRV_INSN_CKNC
! , FRV_INSN_CKN, FRV_INSN_CKP, FRV_INSN_CKV, FRV_INSN_CKNV
! , FRV_INSN_FCKRA, FRV_INSN_FCKNO, FRV_INSN_FCKNE, FRV_INSN_FCKEQ
! , FRV_INSN_FCKLG, FRV_INSN_FCKUE, FRV_INSN_FCKUL, FRV_INSN_FCKGE
! , FRV_INSN_FCKLT, FRV_INSN_FCKUGE, FRV_INSN_FCKUG, FRV_INSN_FCKLE
! , FRV_INSN_FCKGT, FRV_INSN_FCKULE, FRV_INSN_FCKU, FRV_INSN_FCKO
! , FRV_INSN_CCKRA, FRV_INSN_CCKNO, FRV_INSN_CCKEQ, FRV_INSN_CCKNE
! , FRV_INSN_CCKLE, FRV_INSN_CCKGT, FRV_INSN_CCKLT, FRV_INSN_CCKGE
! , FRV_INSN_CCKLS, FRV_INSN_CCKHI, FRV_INSN_CCKC, FRV_INSN_CCKNC
! , FRV_INSN_CCKN, FRV_INSN_CCKP, FRV_INSN_CCKV, FRV_INSN_CCKNV
! , FRV_INSN_CFCKRA, FRV_INSN_CFCKNO, FRV_INSN_CFCKNE, FRV_INSN_CFCKEQ
! , FRV_INSN_CFCKLG, FRV_INSN_CFCKUE, FRV_INSN_CFCKUL, FRV_INSN_CFCKGE
! , FRV_INSN_CFCKLT, FRV_INSN_CFCKUGE, FRV_INSN_CFCKUG, FRV_INSN_CFCKLE
! , FRV_INSN_CFCKGT, FRV_INSN_CFCKULE, FRV_INSN_CFCKU, FRV_INSN_CFCKO
! , FRV_INSN_CJMPL, FRV_INSN_CCALLL, FRV_INSN_ICI, FRV_INSN_DCI
! , FRV_INSN_ICEI, FRV_INSN_DCEI, FRV_INSN_DCF, FRV_INSN_DCEF
! , FRV_INSN_WITLB, FRV_INSN_WDTLB, FRV_INSN_ITLBI, FRV_INSN_DTLBI
! , FRV_INSN_ICPL, FRV_INSN_DCPL, FRV_INSN_ICUL, FRV_INSN_DCUL
! , FRV_INSN_BAR, FRV_INSN_MEMBAR, FRV_INSN_COP1, FRV_INSN_COP2
! , FRV_INSN_CLRGR, FRV_INSN_CLRFR, FRV_INSN_CLRGA, FRV_INSN_CLRFA
! , FRV_INSN_COMMITGR, FRV_INSN_COMMITFR, FRV_INSN_COMMITGA, FRV_INSN_COMMITFA
! , FRV_INSN_FITOS, FRV_INSN_FSTOI, FRV_INSN_FITOD, FRV_INSN_FDTOI
! , FRV_INSN_FDITOS, FRV_INSN_FDSTOI, FRV_INSN_NFDITOS, FRV_INSN_NFDSTOI
! , FRV_INSN_CFITOS, FRV_INSN_CFSTOI, FRV_INSN_NFITOS, FRV_INSN_NFSTOI
! , FRV_INSN_FMOVS, FRV_INSN_FMOVD, FRV_INSN_FDMOVS, FRV_INSN_CFMOVS
! , FRV_INSN_FNEGS, FRV_INSN_FNEGD, FRV_INSN_FDNEGS, FRV_INSN_CFNEGS
! , FRV_INSN_FABSS, FRV_INSN_FABSD, FRV_INSN_FDABSS, FRV_INSN_CFABSS
! , FRV_INSN_FSQRTS, FRV_INSN_FDSQRTS, FRV_INSN_NFDSQRTS, FRV_INSN_FSQRTD
! , FRV_INSN_CFSQRTS, FRV_INSN_NFSQRTS, FRV_INSN_FADDS, FRV_INSN_FSUBS
! , FRV_INSN_FMULS, FRV_INSN_FDIVS, FRV_INSN_FADDD, FRV_INSN_FSUBD
! , FRV_INSN_FMULD, FRV_INSN_FDIVD, FRV_INSN_CFADDS, FRV_INSN_CFSUBS
! , FRV_INSN_CFMULS, FRV_INSN_CFDIVS, FRV_INSN_NFADDS, FRV_INSN_NFSUBS
! , FRV_INSN_NFMULS, FRV_INSN_NFDIVS, FRV_INSN_FCMPS, FRV_INSN_FCMPD
! , FRV_INSN_CFCMPS, FRV_INSN_FDCMPS, FRV_INSN_FMADDS, FRV_INSN_FMSUBS
! , FRV_INSN_FMADDD, FRV_INSN_FMSUBD, FRV_INSN_FDMADDS, FRV_INSN_NFDMADDS
! , FRV_INSN_CFMADDS, FRV_INSN_CFMSUBS, FRV_INSN_NFMADDS, FRV_INSN_NFMSUBS
! , FRV_INSN_FMAS, FRV_INSN_FMSS, FRV_INSN_FDMAS, FRV_INSN_FDMSS
! , FRV_INSN_NFDMAS, FRV_INSN_NFDMSS, FRV_INSN_CFMAS, FRV_INSN_CFMSS
! , FRV_INSN_FMAD, FRV_INSN_FMSD, FRV_INSN_NFMAS, FRV_INSN_NFMSS
! , FRV_INSN_FDADDS, FRV_INSN_FDSUBS, FRV_INSN_FDMULS, FRV_INSN_FDDIVS
! , FRV_INSN_FDSADS, FRV_INSN_FDMULCS, FRV_INSN_NFDMULCS, FRV_INSN_NFDADDS
! , FRV_INSN_NFDSUBS, FRV_INSN_NFDMULS, FRV_INSN_NFDDIVS, FRV_INSN_NFDSADS
! , FRV_INSN_NFDCMPS, FRV_INSN_MHSETLOS, FRV_INSN_MHSETHIS, FRV_INSN_MHDSETS
! , FRV_INSN_MHSETLOH, FRV_INSN_MHSETHIH, FRV_INSN_MHDSETH, FRV_INSN_MAND
! , FRV_INSN_MOR, FRV_INSN_MXOR, FRV_INSN_CMAND, FRV_INSN_CMOR
! , FRV_INSN_CMXOR, FRV_INSN_MNOT, FRV_INSN_CMNOT, FRV_INSN_MROTLI
! , FRV_INSN_MROTRI, FRV_INSN_MWCUT, FRV_INSN_MWCUTI, FRV_INSN_MCUT
! , FRV_INSN_MCUTI, FRV_INSN_MCUTSS, FRV_INSN_MCUTSSI, FRV_INSN_MDCUTSSI
! , FRV_INSN_MAVEH, FRV_INSN_MSLLHI, FRV_INSN_MSRLHI, FRV_INSN_MSRAHI
! , FRV_INSN_MDROTLI, FRV_INSN_MCPLHI, FRV_INSN_MCPLI, FRV_INSN_MSATHS
! , FRV_INSN_MQSATHS, FRV_INSN_MSATHU, FRV_INSN_MCMPSH, FRV_INSN_MCMPUH
! , FRV_INSN_MABSHS, FRV_INSN_MADDHSS, FRV_INSN_MADDHUS, FRV_INSN_MSUBHSS
! , FRV_INSN_MSUBHUS, FRV_INSN_CMADDHSS, FRV_INSN_CMADDHUS, FRV_INSN_CMSUBHSS
! , FRV_INSN_CMSUBHUS, FRV_INSN_MQADDHSS, FRV_INSN_MQADDHUS, FRV_INSN_MQSUBHSS
! , FRV_INSN_MQSUBHUS, FRV_INSN_CMQADDHSS, FRV_INSN_CMQADDHUS, FRV_INSN_CMQSUBHSS
! , FRV_INSN_CMQSUBHUS, FRV_INSN_MADDACCS, FRV_INSN_MSUBACCS, FRV_INSN_MDADDACCS
! , FRV_INSN_MDSUBACCS, FRV_INSN_MASACCS, FRV_INSN_MDASACCS, FRV_INSN_MMULHS
! , FRV_INSN_MMULHU, FRV_INSN_MMULXHS, FRV_INSN_MMULXHU, FRV_INSN_CMMULHS
! , FRV_INSN_CMMULHU, FRV_INSN_MQMULHS, FRV_INSN_MQMULHU, FRV_INSN_MQMULXHS
! , FRV_INSN_MQMULXHU, FRV_INSN_CMQMULHS, FRV_INSN_CMQMULHU, FRV_INSN_MMACHS
! , FRV_INSN_MMACHU, FRV_INSN_MMRDHS, FRV_INSN_MMRDHU, FRV_INSN_CMMACHS
! , FRV_INSN_CMMACHU, FRV_INSN_MQMACHS, FRV_INSN_MQMACHU, FRV_INSN_CMQMACHS
! , FRV_INSN_CMQMACHU, FRV_INSN_MQXMACHS, FRV_INSN_MQXMACXHS, FRV_INSN_MQMACXHS
! , FRV_INSN_MCPXRS, FRV_INSN_MCPXRU, FRV_INSN_MCPXIS, FRV_INSN_MCPXIU
! , FRV_INSN_CMCPXRS, FRV_INSN_CMCPXRU, FRV_INSN_CMCPXIS, FRV_INSN_CMCPXIU
! , FRV_INSN_MQCPXRS, FRV_INSN_MQCPXRU, FRV_INSN_MQCPXIS, FRV_INSN_MQCPXIU
! , FRV_INSN_MEXPDHW, FRV_INSN_CMEXPDHW, FRV_INSN_MEXPDHD, FRV_INSN_CMEXPDHD
! , FRV_INSN_MPACKH, FRV_INSN_MDPACKH, FRV_INSN_MUNPACKH, FRV_INSN_MDUNPACKH
! , FRV_INSN_MBTOH, FRV_INSN_CMBTOH, FRV_INSN_MHTOB, FRV_INSN_CMHTOB
! , FRV_INSN_MBTOHE, FRV_INSN_CMBTOHE, FRV_INSN_MNOP, FRV_INSN_MCLRACC_0
! , FRV_INSN_MCLRACC_1, FRV_INSN_MRDACC, FRV_INSN_MRDACCG, FRV_INSN_MWTACC
! , FRV_INSN_MWTACCG, FRV_INSN_MCOP1, FRV_INSN_MCOP2, FRV_INSN_FNOP
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */
Index: sim/frv/arch.h
===================================================================
RCS file: /cvs/src/src/sim/frv/arch.h,v
retrieving revision 1.2
diff -c -p -r1.2 arch.h
*** sim/frv/arch.h 12 Sep 2003 22:05:21 -0000 1.2
--- sim/frv/arch.h 24 Sep 2003 18:52:20 -0000
*************** typedef enum model_type {
*** 37,67 ****
/* Enum declaration for unit types. */
typedef enum unit_type {
! UNIT_NONE, UNIT_FRV_U_EXEC, UNIT_FR500_U_DCUL, UNIT_FR500_U_ICUL
! , UNIT_FR500_U_DCPL, UNIT_FR500_U_ICPL, UNIT_FR500_U_DCF, UNIT_FR500_U_DCI
! , UNIT_FR500_U_ICI, UNIT_FR500_U_MEMBAR, UNIT_FR500_U_BARRIER, UNIT_FR500_U_MEDIA_DUAL_BTOHE
! , UNIT_FR500_U_MEDIA_DUAL_HTOB, UNIT_FR500_U_MEDIA_DUAL_BTOH, UNIT_FR500_U_MEDIA_DUAL_UNPACK, UNIT_FR500_U_MEDIA_DUAL_EXPAND
! , UNIT_FR500_U_MEDIA_QUAD_COMPLEX, UNIT_FR500_U_MEDIA_QUAD_MUL, UNIT_FR500_U_MEDIA_DUAL_MUL, UNIT_FR500_U_MEDIA_QUAD_ARITH
! , UNIT_FR500_U_MEDIA, UNIT_FR500_U_FLOAT_DUAL_CONVERT, UNIT_FR500_U_FLOAT_CONVERT, UNIT_FR500_U_FLOAT_DUAL_COMPARE
! , UNIT_FR500_U_FLOAT_COMPARE, UNIT_FR500_U_FLOAT_DUAL_SQRT, UNIT_FR500_U_FLOAT_SQRT, UNIT_FR500_U_FLOAT_DIV
! , UNIT_FR500_U_FLOAT_DUAL_ARITH, UNIT_FR500_U_FLOAT_ARITH, UNIT_FR500_U_GR2SPR, UNIT_FR500_U_GR2FR
! , UNIT_FR500_U_SPR2GR, UNIT_FR500_U_FR2GR, UNIT_FR500_U_FR2FR, UNIT_FR500_U_SWAP
! , UNIT_FR500_U_FR_R_STORE, UNIT_FR500_U_FR_STORE, UNIT_FR500_U_FR_LOAD, UNIT_FR500_U_GR_R_STORE
! , UNIT_FR500_U_GR_STORE, UNIT_FR500_U_GR_LOAD, UNIT_FR500_U_SET_HILO, UNIT_FR500_U_CLRFR
! , UNIT_FR500_U_CLRGR, UNIT_FR500_U_CHECK, UNIT_FR500_U_TRAP, UNIT_FR500_U_BRANCH
! , UNIT_FR500_U_IDIV, UNIT_FR500_U_IMUL, UNIT_FR500_U_INTEGER, UNIT_FR500_U_EXEC
! , UNIT_TOMCAT_U_EXEC, UNIT_FR400_U_DCUL, UNIT_FR400_U_ICUL, UNIT_FR400_U_DCPL
! , UNIT_FR400_U_ICPL, UNIT_FR400_U_DCF, UNIT_FR400_U_DCI, UNIT_FR400_U_ICI
! , UNIT_FR400_U_MEMBAR, UNIT_FR400_U_BARRIER, UNIT_FR400_U_MEDIA_DUAL_HTOB, UNIT_FR400_U_MEDIA_DUAL_EXPAND
! , UNIT_FR400_U_MEDIA_7, UNIT_FR400_U_MEDIA_6, UNIT_FR400_U_MEDIA_4_ACC_DUAL, UNIT_FR400_U_MEDIA_4_ACCG
! , UNIT_FR400_U_MEDIA_4, UNIT_FR400_U_MEDIA_3_QUAD, UNIT_FR400_U_MEDIA_3_DUAL, UNIT_FR400_U_MEDIA_3
! , UNIT_FR400_U_MEDIA_2_ADD_SUB_DUAL, UNIT_FR400_U_MEDIA_2_ADD_SUB, UNIT_FR400_U_MEDIA_2_ACC_DUAL, UNIT_FR400_U_MEDIA_2_ACC
! , UNIT_FR400_U_MEDIA_2_QUAD, UNIT_FR400_U_MEDIA_2, UNIT_FR400_U_MEDIA_HILO, UNIT_FR400_U_MEDIA_1_QUAD
! , UNIT_FR400_U_MEDIA_1, UNIT_FR400_U_GR2SPR, UNIT_FR400_U_GR2FR, UNIT_FR400_U_SPR2GR
! , UNIT_FR400_U_FR2GR, UNIT_FR400_U_SWAP, UNIT_FR400_U_FR_STORE, UNIT_FR400_U_FR_LOAD
! , UNIT_FR400_U_GR_STORE, UNIT_FR400_U_GR_LOAD, UNIT_FR400_U_SET_HILO, UNIT_FR400_U_CHECK
! , UNIT_FR400_U_TRAP, UNIT_FR400_U_BRANCH, UNIT_FR400_U_IDIV, UNIT_FR400_U_IMUL
! , UNIT_FR400_U_INTEGER, UNIT_FR400_U_EXEC, UNIT_SIMPLE_U_EXEC, UNIT_MAX
} UNIT_TYPE;
#define MAX_UNITS (1)
--- 37,68 ----
/* Enum declaration for unit types. */
typedef enum unit_type {
! UNIT_NONE, UNIT_FRV_U_EXEC, UNIT_FR500_U_COMMIT, UNIT_FR500_U_DCUL
! , UNIT_FR500_U_ICUL, UNIT_FR500_U_DCPL, UNIT_FR500_U_ICPL, UNIT_FR500_U_DCF
! , UNIT_FR500_U_DCI, UNIT_FR500_U_ICI, UNIT_FR500_U_MEMBAR, UNIT_FR500_U_BARRIER
! , UNIT_FR500_U_MEDIA_DUAL_BTOHE, UNIT_FR500_U_MEDIA_DUAL_HTOB, UNIT_FR500_U_MEDIA_DUAL_BTOH, UNIT_FR500_U_MEDIA_DUAL_UNPACK
! , UNIT_FR500_U_MEDIA_DUAL_EXPAND, UNIT_FR500_U_MEDIA_QUAD_COMPLEX, UNIT_FR500_U_MEDIA_QUAD_MUL, UNIT_FR500_U_MEDIA_DUAL_MUL
! , UNIT_FR500_U_MEDIA_QUAD_ARITH, UNIT_FR500_U_MEDIA, UNIT_FR500_U_FLOAT_DUAL_CONVERT, UNIT_FR500_U_FLOAT_CONVERT
! , UNIT_FR500_U_FLOAT_DUAL_COMPARE, UNIT_FR500_U_FLOAT_COMPARE, UNIT_FR500_U_FLOAT_DUAL_SQRT, UNIT_FR500_U_FLOAT_SQRT
! , UNIT_FR500_U_FLOAT_DIV, UNIT_FR500_U_FLOAT_DUAL_ARITH, UNIT_FR500_U_FLOAT_ARITH, UNIT_FR500_U_GR2SPR
! , UNIT_FR500_U_GR2FR, UNIT_FR500_U_SPR2GR, UNIT_FR500_U_FR2GR, UNIT_FR500_U_FR2FR
! , UNIT_FR500_U_SWAP, UNIT_FR500_U_FR_R_STORE, UNIT_FR500_U_FR_STORE, UNIT_FR500_U_FR_LOAD
! , UNIT_FR500_U_GR_R_STORE, UNIT_FR500_U_GR_STORE, UNIT_FR500_U_GR_LOAD, UNIT_FR500_U_SET_HILO
! , UNIT_FR500_U_CLRFR, UNIT_FR500_U_CLRGR, UNIT_FR500_U_CHECK, UNIT_FR500_U_TRAP
! , UNIT_FR500_U_BRANCH, UNIT_FR500_U_IDIV, UNIT_FR500_U_IMUL, UNIT_FR500_U_INTEGER
! , UNIT_FR500_U_EXEC, UNIT_TOMCAT_U_EXEC, UNIT_FR400_U_DCUL, UNIT_FR400_U_ICUL
! , UNIT_FR400_U_DCPL, UNIT_FR400_U_ICPL, UNIT_FR400_U_DCF, UNIT_FR400_U_DCI
! , UNIT_FR400_U_ICI, UNIT_FR400_U_MEMBAR, UNIT_FR400_U_BARRIER, UNIT_FR400_U_MEDIA_DUAL_HTOB
! , UNIT_FR400_U_MEDIA_DUAL_EXPAND, UNIT_FR400_U_MEDIA_7, UNIT_FR400_U_MEDIA_6, UNIT_FR400_U_MEDIA_4_ACC_DUAL
! , UNIT_FR400_U_MEDIA_4_ACCG, UNIT_FR400_U_MEDIA_4, UNIT_FR400_U_MEDIA_3_QUAD, UNIT_FR400_U_MEDIA_3_DUAL
! , UNIT_FR400_U_MEDIA_3, UNIT_FR400_U_MEDIA_2_ADD_SUB_DUAL, UNIT_FR400_U_MEDIA_2_ADD_SUB, UNIT_FR400_U_MEDIA_2_ACC_DUAL
! , UNIT_FR400_U_MEDIA_2_ACC, UNIT_FR400_U_MEDIA_2_QUAD, UNIT_FR400_U_MEDIA_2, UNIT_FR400_U_MEDIA_HILO
! , UNIT_FR400_U_MEDIA_1_QUAD, UNIT_FR400_U_MEDIA_1, UNIT_FR400_U_GR2SPR, UNIT_FR400_U_GR2FR
! , UNIT_FR400_U_SPR2GR, UNIT_FR400_U_FR2GR, UNIT_FR400_U_SWAP, UNIT_FR400_U_FR_STORE
! , UNIT_FR400_U_FR_LOAD, UNIT_FR400_U_GR_STORE, UNIT_FR400_U_GR_LOAD, UNIT_FR400_U_SET_HILO
! , UNIT_FR400_U_CHECK, UNIT_FR400_U_TRAP, UNIT_FR400_U_BRANCH, UNIT_FR400_U_IDIV
! , UNIT_FR400_U_IMUL, UNIT_FR400_U_INTEGER, UNIT_FR400_U_EXEC, UNIT_SIMPLE_U_EXEC
! , UNIT_MAX
} UNIT_TYPE;
#define MAX_UNITS (1)
Index: sim/frv/cpu.h
===================================================================
RCS file: /cvs/src/src/sim/frv/cpu.h,v
retrieving revision 1.2
diff -c -p -r1.2 cpu.h
*** sim/frv/cpu.h 3 Sep 2003 23:12:21 -0000 1.2
--- sim/frv/cpu.h 24 Sep 2003 18:52:20 -0000
*************** frvbf_h_spr_set_handler (current_cpu, (i
*** 140,146 ****
UQI h_iccr[4];
#define GET_H_ICCR(a1) CPU (h_iccr)[a1]
#define SET_H_ICCR(a1, x) (CPU (h_iccr)[a1] = (x))
! /* Integer condition code registers */
UQI h_fccr[4];
#define GET_H_FCCR(a1) CPU (h_fccr)[a1]
#define SET_H_FCCR(a1, x) (CPU (h_fccr)[a1] = (x))
--- 140,146 ----
UQI h_iccr[4];
#define GET_H_ICCR(a1) CPU (h_iccr)[a1]
#define SET_H_ICCR(a1, x) (CPU (h_iccr)[a1] = (x))
! /* Floating point condition code registers */
UQI h_fccr[4];
#define GET_H_FCCR(a1) CPU (h_fccr)[a1]
#define SET_H_FCCR(a1, x) (CPU (h_fccr)[a1] = (x))
*************** union sem_fields {
*** 419,430 ****
unsigned char out_GRklo;
} sfmt_setlo;
struct { /* */
- UINT f_ACCGk;
- UINT f_FRi;
- unsigned char in_FRinti;
- unsigned char out_ACCGk;
- } sfmt_mwtaccg;
- struct { /* */
UINT f_ACCGi;
UINT f_FRk;
unsigned char in_ACCGi;
--- 419,424 ----
*************** union sem_fields {
*** 484,489 ****
--- 478,490 ----
unsigned short out_spr;
unsigned char in_GRj;
} sfmt_movgs;
+ struct { /* */
+ UINT f_ACCGk;
+ UINT f_FRi;
+ unsigned char in_ACCGk;
+ unsigned char in_FRinti;
+ unsigned char out_ACCGk;
+ } sfmt_mwtaccg;
struct { /* */
INT f_s6;
UINT f_ACC40Si;
Index: sim/frv/decode.c
===================================================================
RCS file: /cvs/src/src/sim/frv/decode.c,v
retrieving revision 1.3
diff -c -p -r1.3 decode.c
*** sim/frv/decode.c 12 Sep 2003 22:05:21 -0000 1.3
--- sim/frv/decode.c 24 Sep 2003 18:52:21 -0000
*************** static const struct insn_sem frvbf_insn_
*** 208,214 ****
{ FRV_INSN_NLDDFI, FRVBF_INSN_NLDDFI, FRVBF_SFMT_NLDDFI },
{ FRV_INSN_LDQI, FRVBF_INSN_LDQI, FRVBF_SFMT_LDQI },
{ FRV_INSN_LDQFI, FRVBF_INSN_LDQFI, FRVBF_SFMT_LDQFI },
- { FRV_INSN_NLDQI, FRVBF_INSN_NLDQI, FRVBF_SFMT_NLDQI },
{ FRV_INSN_NLDQFI, FRVBF_INSN_NLDQFI, FRVBF_SFMT_NLDQFI },
{ FRV_INSN_STB, FRVBF_INSN_STB, FRVBF_SFMT_STB },
{ FRV_INSN_STH, FRVBF_INSN_STH, FRVBF_SFMT_STB },
--- 208,213 ----
*************** frvbf_decode (SIM_CPU *current_cpu, IADD
*** 1409,1415 ****
case 67 : itype = FRVBF_INSN_NLDUHI; goto extract_sfmt_nldsbi;
case 68 : itype = FRVBF_INSN_NLDI; goto extract_sfmt_nldsbi;
case 69 : itype = FRVBF_INSN_NLDDI; goto extract_sfmt_nlddi;
- case 70 : itype = FRVBF_INSN_NLDQI; goto extract_sfmt_nldqi;
case 71 : itype = FRVBF_INSN_SCANI; goto extract_sfmt_addi;
case 72 : itype = FRVBF_INSN_NLDBFI; goto extract_sfmt_nldbfi;
case 73 : itype = FRVBF_INSN_NLDHFI; goto extract_sfmt_nldbfi;
--- 1408,1413 ----
*************** frvbf_decode (SIM_CPU *current_cpu, IADD
*** 4383,4418 ****
return idesc;
}
- extract_sfmt_nldqi:
- {
- const IDESC *idesc = &frvbf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
- #define FLD(f) abuf->fields.sfmt_stdi.f
- UINT f_GRk;
- UINT f_GRi;
- INT f_d12;
-
- f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
- f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
- f_d12 = EXTRACT_LSB0_INT (insn, 32, 11, 12);
-
- /* Record the fields for the semantic handler. */
- FLD (f_GRi) = f_GRi;
- FLD (f_d12) = f_d12;
- FLD (f_GRk) = f_GRk;
- TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nldqi", "f_GRi 0x%x", 'x', f_GRi, "f_d12 0x%x", 'x', f_d12, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
-
- #if WITH_PROFILE_MODEL_P
- /* Record the fields for profiling. */
- if (PROFILE_MODEL_P (current_cpu))
- {
- FLD (in_GRi) = f_GRi;
- }
- #endif
- #undef FLD
- return idesc;
- }
-
extract_sfmt_nldqfi:
{
const IDESC *idesc = &frvbf_insn_data[itype];
--- 4381,4386 ----
*************** frvbf_decode (SIM_CPU *current_cpu, IADD
*** 10999,11012 ****
f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
/* Record the fields for the semantic handler. */
- FLD (f_FRi) = f_FRi;
FLD (f_ACCGk) = f_ACCGk;
! TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mwtaccg", "f_FRi 0x%x", 'x', f_FRi, "f_ACCGk 0x%x", 'x', f_ACCGk, (char *) 0));
#if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_FRinti) = f_FRi;
FLD (out_ACCGk) = f_ACCGk;
}
--- 10967,10981 ----
f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
/* Record the fields for the semantic handler. */
FLD (f_ACCGk) = f_ACCGk;
! FLD (f_FRi) = f_FRi;
! TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mwtaccg", "f_ACCGk 0x%x", 'x', f_ACCGk, "f_FRi 0x%x", 'x', f_FRi, (char *) 0));
#if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
+ FLD (in_ACCGk) = f_ACCGk;
FLD (in_FRinti) = f_FRi;
FLD (out_ACCGk) = f_ACCGk;
}
Index: sim/frv/decode.h
===================================================================
RCS file: /cvs/src/src/sim/frv/decode.h,v
retrieving revision 1.3
diff -c -p -r1.3 decode.h
*** sim/frv/decode.h 12 Sep 2003 22:05:21 -0000 1.3
--- sim/frv/decode.h 24 Sep 2003 18:52:21 -0000
*************** typedef enum frvbf_insn_type {
*** 76,226 ****
, FRVBF_INSN_NLDSHI, FRVBF_INSN_NLDUHI, FRVBF_INSN_NLDI, FRVBF_INSN_NLDBFI
, FRVBF_INSN_NLDHFI, FRVBF_INSN_NLDFI, FRVBF_INSN_LDDI, FRVBF_INSN_LDDFI
, FRVBF_INSN_NLDDI, FRVBF_INSN_NLDDFI, FRVBF_INSN_LDQI, FRVBF_INSN_LDQFI
! , FRVBF_INSN_NLDQI, FRVBF_INSN_NLDQFI, FRVBF_INSN_STB, FRVBF_INSN_STH
! , FRVBF_INSN_ST, FRVBF_INSN_STBF, FRVBF_INSN_STHF, FRVBF_INSN_STF
! , FRVBF_INSN_STC, FRVBF_INSN_RSTB, FRVBF_INSN_RSTH, FRVBF_INSN_RST
! , FRVBF_INSN_RSTBF, FRVBF_INSN_RSTHF, FRVBF_INSN_RSTF, FRVBF_INSN_STD
! , FRVBF_INSN_STDF, FRVBF_INSN_STDC, FRVBF_INSN_RSTD, FRVBF_INSN_RSTDF
! , FRVBF_INSN_STQ, FRVBF_INSN_STQF, FRVBF_INSN_STQC, FRVBF_INSN_RSTQ
! , FRVBF_INSN_RSTQF, FRVBF_INSN_STBU, FRVBF_INSN_STHU, FRVBF_INSN_STU
! , FRVBF_INSN_STBFU, FRVBF_INSN_STHFU, FRVBF_INSN_STFU, FRVBF_INSN_STCU
! , FRVBF_INSN_STDU, FRVBF_INSN_STDFU, FRVBF_INSN_STDCU, FRVBF_INSN_STQU
! , FRVBF_INSN_STQFU, FRVBF_INSN_STQCU, FRVBF_INSN_CLDSB, FRVBF_INSN_CLDUB
! , FRVBF_INSN_CLDSH, FRVBF_INSN_CLDUH, FRVBF_INSN_CLD, FRVBF_INSN_CLDBF
! , FRVBF_INSN_CLDHF, FRVBF_INSN_CLDF, FRVBF_INSN_CLDD, FRVBF_INSN_CLDDF
! , FRVBF_INSN_CLDQ, FRVBF_INSN_CLDSBU, FRVBF_INSN_CLDUBU, FRVBF_INSN_CLDSHU
! , FRVBF_INSN_CLDUHU, FRVBF_INSN_CLDU, FRVBF_INSN_CLDBFU, FRVBF_INSN_CLDHFU
! , FRVBF_INSN_CLDFU, FRVBF_INSN_CLDDU, FRVBF_INSN_CLDDFU, FRVBF_INSN_CLDQU
! , FRVBF_INSN_CSTB, FRVBF_INSN_CSTH, FRVBF_INSN_CST, FRVBF_INSN_CSTBF
! , FRVBF_INSN_CSTHF, FRVBF_INSN_CSTF, FRVBF_INSN_CSTD, FRVBF_INSN_CSTDF
! , FRVBF_INSN_CSTQ, FRVBF_INSN_CSTBU, FRVBF_INSN_CSTHU, FRVBF_INSN_CSTU
! , FRVBF_INSN_CSTBFU, FRVBF_INSN_CSTHFU, FRVBF_INSN_CSTFU, FRVBF_INSN_CSTDU
! , FRVBF_INSN_CSTDFU, FRVBF_INSN_STBI, FRVBF_INSN_STHI, FRVBF_INSN_STI
! , FRVBF_INSN_STBFI, FRVBF_INSN_STHFI, FRVBF_INSN_STFI, FRVBF_INSN_STDI
! , FRVBF_INSN_STDFI, FRVBF_INSN_STQI, FRVBF_INSN_STQFI, FRVBF_INSN_SWAP
! , FRVBF_INSN_SWAPI, FRVBF_INSN_CSWAP, FRVBF_INSN_MOVGF, FRVBF_INSN_MOVFG
! , FRVBF_INSN_MOVGFD, FRVBF_INSN_MOVFGD, FRVBF_INSN_MOVGFQ, FRVBF_INSN_MOVFGQ
! , FRVBF_INSN_CMOVGF, FRVBF_INSN_CMOVFG, FRVBF_INSN_CMOVGFD, FRVBF_INSN_CMOVFGD
! , FRVBF_INSN_MOVGS, FRVBF_INSN_MOVSG, FRVBF_INSN_BRA, FRVBF_INSN_BNO
! , FRVBF_INSN_BEQ, FRVBF_INSN_BNE, FRVBF_INSN_BLE, FRVBF_INSN_BGT
! , FRVBF_INSN_BLT, FRVBF_INSN_BGE, FRVBF_INSN_BLS, FRVBF_INSN_BHI
! , FRVBF_INSN_BC, FRVBF_INSN_BNC, FRVBF_INSN_BN, FRVBF_INSN_BP
! , FRVBF_INSN_BV, FRVBF_INSN_BNV, FRVBF_INSN_FBRA, FRVBF_INSN_FBNO
! , FRVBF_INSN_FBNE, FRVBF_INSN_FBEQ, FRVBF_INSN_FBLG, FRVBF_INSN_FBUE
! , FRVBF_INSN_FBUL, FRVBF_INSN_FBGE, FRVBF_INSN_FBLT, FRVBF_INSN_FBUGE
! , FRVBF_INSN_FBUG, FRVBF_INSN_FBLE, FRVBF_INSN_FBGT, FRVBF_INSN_FBULE
! , FRVBF_INSN_FBU, FRVBF_INSN_FBO, FRVBF_INSN_BCTRLR, FRVBF_INSN_BRALR
! , FRVBF_INSN_BNOLR, FRVBF_INSN_BEQLR, FRVBF_INSN_BNELR, FRVBF_INSN_BLELR
! , FRVBF_INSN_BGTLR, FRVBF_INSN_BLTLR, FRVBF_INSN_BGELR, FRVBF_INSN_BLSLR
! , FRVBF_INSN_BHILR, FRVBF_INSN_BCLR, FRVBF_INSN_BNCLR, FRVBF_INSN_BNLR
! , FRVBF_INSN_BPLR, FRVBF_INSN_BVLR, FRVBF_INSN_BNVLR, FRVBF_INSN_FBRALR
! , FRVBF_INSN_FBNOLR, FRVBF_INSN_FBEQLR, FRVBF_INSN_FBNELR, FRVBF_INSN_FBLGLR
! , FRVBF_INSN_FBUELR, FRVBF_INSN_FBULLR, FRVBF_INSN_FBGELR, FRVBF_INSN_FBLTLR
! , FRVBF_INSN_FBUGELR, FRVBF_INSN_FBUGLR, FRVBF_INSN_FBLELR, FRVBF_INSN_FBGTLR
! , FRVBF_INSN_FBULELR, FRVBF_INSN_FBULR, FRVBF_INSN_FBOLR, FRVBF_INSN_BCRALR
! , FRVBF_INSN_BCNOLR, FRVBF_INSN_BCEQLR, FRVBF_INSN_BCNELR, FRVBF_INSN_BCLELR
! , FRVBF_INSN_BCGTLR, FRVBF_INSN_BCLTLR, FRVBF_INSN_BCGELR, FRVBF_INSN_BCLSLR
! , FRVBF_INSN_BCHILR, FRVBF_INSN_BCCLR, FRVBF_INSN_BCNCLR, FRVBF_INSN_BCNLR
! , FRVBF_INSN_BCPLR, FRVBF_INSN_BCVLR, FRVBF_INSN_BCNVLR, FRVBF_INSN_FCBRALR
! , FRVBF_INSN_FCBNOLR, FRVBF_INSN_FCBEQLR, FRVBF_INSN_FCBNELR, FRVBF_INSN_FCBLGLR
! , FRVBF_INSN_FCBUELR, FRVBF_INSN_FCBULLR, FRVBF_INSN_FCBGELR, FRVBF_INSN_FCBLTLR
! , FRVBF_INSN_FCBUGELR, FRVBF_INSN_FCBUGLR, FRVBF_INSN_FCBLELR, FRVBF_INSN_FCBGTLR
! , FRVBF_INSN_FCBULELR, FRVBF_INSN_FCBULR, FRVBF_INSN_FCBOLR, FRVBF_INSN_JMPL
! , FRVBF_INSN_CALLL, FRVBF_INSN_JMPIL, FRVBF_INSN_CALLIL, FRVBF_INSN_CALL
! , FRVBF_INSN_RETT, FRVBF_INSN_REI, FRVBF_INSN_TRA, FRVBF_INSN_TNO
! , FRVBF_INSN_TEQ, FRVBF_INSN_TNE, FRVBF_INSN_TLE, FRVBF_INSN_TGT
! , FRVBF_INSN_TLT, FRVBF_INSN_TGE, FRVBF_INSN_TLS, FRVBF_INSN_THI
! , FRVBF_INSN_TC, FRVBF_INSN_TNC, FRVBF_INSN_TN, FRVBF_INSN_TP
! , FRVBF_INSN_TV, FRVBF_INSN_TNV, FRVBF_INSN_FTRA, FRVBF_INSN_FTNO
! , FRVBF_INSN_FTNE, FRVBF_INSN_FTEQ, FRVBF_INSN_FTLG, FRVBF_INSN_FTUE
! , FRVBF_INSN_FTUL, FRVBF_INSN_FTGE, FRVBF_INSN_FTLT, FRVBF_INSN_FTUGE
! , FRVBF_INSN_FTUG, FRVBF_INSN_FTLE, FRVBF_INSN_FTGT, FRVBF_INSN_FTULE
! , FRVBF_INSN_FTU, FRVBF_INSN_FTO, FRVBF_INSN_TIRA, FRVBF_INSN_TINO
! , FRVBF_INSN_TIEQ, FRVBF_INSN_TINE, FRVBF_INSN_TILE, FRVBF_INSN_TIGT
! , FRVBF_INSN_TILT, FRVBF_INSN_TIGE, FRVBF_INSN_TILS, FRVBF_INSN_TIHI
! , FRVBF_INSN_TIC, FRVBF_INSN_TINC, FRVBF_INSN_TIN, FRVBF_INSN_TIP
! , FRVBF_INSN_TIV, FRVBF_INSN_TINV, FRVBF_INSN_FTIRA, FRVBF_INSN_FTINO
! , FRVBF_INSN_FTINE, FRVBF_INSN_FTIEQ, FRVBF_INSN_FTILG, FRVBF_INSN_FTIUE
! , FRVBF_INSN_FTIUL, FRVBF_INSN_FTIGE, FRVBF_INSN_FTILT, FRVBF_INSN_FTIUGE
! , FRVBF_INSN_FTIUG, FRVBF_INSN_FTILE, FRVBF_INSN_FTIGT, FRVBF_INSN_FTIULE
! , FRVBF_INSN_FTIU, FRVBF_INSN_FTIO, FRVBF_INSN_BREAK, FRVBF_INSN_MTRAP
! , FRVBF_INSN_ANDCR, FRVBF_INSN_ORCR, FRVBF_INSN_XORCR, FRVBF_INSN_NANDCR
! , FRVBF_INSN_NORCR, FRVBF_INSN_ANDNCR, FRVBF_INSN_ORNCR, FRVBF_INSN_NANDNCR
! , FRVBF_INSN_NORNCR, FRVBF_INSN_NOTCR, FRVBF_INSN_CKRA, FRVBF_INSN_CKNO
! , FRVBF_INSN_CKEQ, FRVBF_INSN_CKNE, FRVBF_INSN_CKLE, FRVBF_INSN_CKGT
! , FRVBF_INSN_CKLT, FRVBF_INSN_CKGE, FRVBF_INSN_CKLS, FRVBF_INSN_CKHI
! , FRVBF_INSN_CKC, FRVBF_INSN_CKNC, FRVBF_INSN_CKN, FRVBF_INSN_CKP
! , FRVBF_INSN_CKV, FRVBF_INSN_CKNV, FRVBF_INSN_FCKRA, FRVBF_INSN_FCKNO
! , FRVBF_INSN_FCKNE, FRVBF_INSN_FCKEQ, FRVBF_INSN_FCKLG, FRVBF_INSN_FCKUE
! , FRVBF_INSN_FCKUL, FRVBF_INSN_FCKGE, FRVBF_INSN_FCKLT, FRVBF_INSN_FCKUGE
! , FRVBF_INSN_FCKUG, FRVBF_INSN_FCKLE, FRVBF_INSN_FCKGT, FRVBF_INSN_FCKULE
! , FRVBF_INSN_FCKU, FRVBF_INSN_FCKO, FRVBF_INSN_CCKRA, FRVBF_INSN_CCKNO
! , FRVBF_INSN_CCKEQ, FRVBF_INSN_CCKNE, FRVBF_INSN_CCKLE, FRVBF_INSN_CCKGT
! , FRVBF_INSN_CCKLT, FRVBF_INSN_CCKGE, FRVBF_INSN_CCKLS, FRVBF_INSN_CCKHI
! , FRVBF_INSN_CCKC, FRVBF_INSN_CCKNC, FRVBF_INSN_CCKN, FRVBF_INSN_CCKP
! , FRVBF_INSN_CCKV, FRVBF_INSN_CCKNV, FRVBF_INSN_CFCKRA, FRVBF_INSN_CFCKNO
! , FRVBF_INSN_CFCKNE, FRVBF_INSN_CFCKEQ, FRVBF_INSN_CFCKLG, FRVBF_INSN_CFCKUE
! , FRVBF_INSN_CFCKUL, FRVBF_INSN_CFCKGE, FRVBF_INSN_CFCKLT, FRVBF_INSN_CFCKUGE
! , FRVBF_INSN_CFCKUG, FRVBF_INSN_CFCKLE, FRVBF_INSN_CFCKGT, FRVBF_INSN_CFCKULE
! , FRVBF_INSN_CFCKU, FRVBF_INSN_CFCKO, FRVBF_INSN_CJMPL, FRVBF_INSN_CCALLL
! , FRVBF_INSN_ICI, FRVBF_INSN_DCI, FRVBF_INSN_ICEI, FRVBF_INSN_DCEI
! , FRVBF_INSN_DCF, FRVBF_INSN_DCEF, FRVBF_INSN_WITLB, FRVBF_INSN_WDTLB
! , FRVBF_INSN_ITLBI, FRVBF_INSN_DTLBI, FRVBF_INSN_ICPL, FRVBF_INSN_DCPL
! , FRVBF_INSN_ICUL, FRVBF_INSN_DCUL, FRVBF_INSN_BAR, FRVBF_INSN_MEMBAR
! , FRVBF_INSN_COP1, FRVBF_INSN_COP2, FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR
! , FRVBF_INSN_CLRGA, FRVBF_INSN_CLRFA, FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR
! , FRVBF_INSN_COMMITGA, FRVBF_INSN_COMMITFA, FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI
! , FRVBF_INSN_FITOD, FRVBF_INSN_FDTOI, FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI
! , FRVBF_INSN_NFDITOS, FRVBF_INSN_NFDSTOI, FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI
! , FRVBF_INSN_NFITOS, FRVBF_INSN_NFSTOI, FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD
! , FRVBF_INSN_FDMOVS, FRVBF_INSN_CFMOVS, FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD
! , FRVBF_INSN_FDNEGS, FRVBF_INSN_CFNEGS, FRVBF_INSN_FABSS, FRVBF_INSN_FABSD
! , FRVBF_INSN_FDABSS, FRVBF_INSN_CFABSS, FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS
! , FRVBF_INSN_NFDSQRTS, FRVBF_INSN_FSQRTD, FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS
! , FRVBF_INSN_FADDS, FRVBF_INSN_FSUBS, FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS
! , FRVBF_INSN_FADDD, FRVBF_INSN_FSUBD, FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD
! , FRVBF_INSN_CFADDS, FRVBF_INSN_CFSUBS, FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS
! , FRVBF_INSN_NFADDS, FRVBF_INSN_NFSUBS, FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS
! , FRVBF_INSN_FCMPS, FRVBF_INSN_FCMPD, FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS
! , FRVBF_INSN_FMADDS, FRVBF_INSN_FMSUBS, FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD
! , FRVBF_INSN_FDMADDS, FRVBF_INSN_NFDMADDS, FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS
! , FRVBF_INSN_NFMADDS, FRVBF_INSN_NFMSUBS, FRVBF_INSN_FMAS, FRVBF_INSN_FMSS
! , FRVBF_INSN_FDMAS, FRVBF_INSN_FDMSS, FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS
! , FRVBF_INSN_CFMAS, FRVBF_INSN_CFMSS, FRVBF_INSN_FMAD, FRVBF_INSN_FMSD
! , FRVBF_INSN_NFMAS, FRVBF_INSN_NFMSS, FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS
! , FRVBF_INSN_FDMULS, FRVBF_INSN_FDDIVS, FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS
! , FRVBF_INSN_NFDMULCS, FRVBF_INSN_NFDADDS, FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS
! , FRVBF_INSN_NFDDIVS, FRVBF_INSN_NFDSADS, FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS
! , FRVBF_INSN_MHSETHIS, FRVBF_INSN_MHDSETS, FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH
! , FRVBF_INSN_MHDSETH, FRVBF_INSN_MAND, FRVBF_INSN_MOR, FRVBF_INSN_MXOR
! , FRVBF_INSN_CMAND, FRVBF_INSN_CMOR, FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT
! , FRVBF_INSN_CMNOT, FRVBF_INSN_MROTLI, FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT
! , FRVBF_INSN_MWCUTI, FRVBF_INSN_MCUT, FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS
! , FRVBF_INSN_MCUTSSI, FRVBF_INSN_MDCUTSSI, FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI
! , FRVBF_INSN_MSRLHI, FRVBF_INSN_MSRAHI, FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI
! , FRVBF_INSN_MCPLI, FRVBF_INSN_MSATHS, FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU
! , FRVBF_INSN_MCMPSH, FRVBF_INSN_MCMPUH, FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS
! , FRVBF_INSN_MADDHUS, FRVBF_INSN_MSUBHSS, FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS
! , FRVBF_INSN_CMADDHUS, FRVBF_INSN_CMSUBHSS, FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS
! , FRVBF_INSN_MQADDHUS, FRVBF_INSN_MQSUBHSS, FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS
! , FRVBF_INSN_CMQADDHUS, FRVBF_INSN_CMQSUBHSS, FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MADDACCS
! , FRVBF_INSN_MSUBACCS, FRVBF_INSN_MDADDACCS, FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS
! , FRVBF_INSN_MDASACCS, FRVBF_INSN_MMULHS, FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS
! , FRVBF_INSN_MMULXHU, FRVBF_INSN_CMMULHS, FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS
! , FRVBF_INSN_MQMULHU, FRVBF_INSN_MQMULXHS, FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS
! , FRVBF_INSN_CMQMULHU, FRVBF_INSN_MMACHS, FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS
! , FRVBF_INSN_MMRDHU, FRVBF_INSN_CMMACHS, FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS
! , FRVBF_INSN_MQMACHU, FRVBF_INSN_CMQMACHS, FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS
! , FRVBF_INSN_MQXMACXHS, FRVBF_INSN_MQMACXHS, FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU
! , FRVBF_INSN_MCPXIS, FRVBF_INSN_MCPXIU, FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU
! , FRVBF_INSN_CMCPXIS, FRVBF_INSN_CMCPXIU, FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU
! , FRVBF_INSN_MQCPXIS, FRVBF_INSN_MQCPXIU, FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW
! , FRVBF_INSN_MEXPDHD, FRVBF_INSN_CMEXPDHD, FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH
! , FRVBF_INSN_MUNPACKH, FRVBF_INSN_MDUNPACKH, FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH
! , FRVBF_INSN_MHTOB, FRVBF_INSN_CMHTOB, FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE
! , FRVBF_INSN_MNOP, FRVBF_INSN_MCLRACC_0, FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC
! , FRVBF_INSN_MRDACCG, FRVBF_INSN_MWTACC, FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1
! , FRVBF_INSN_MCOP2, FRVBF_INSN_FNOP, FRVBF_INSN__MAX
} FRVBF_INSN_TYPE;
/* Enum declaration for semantic formats in cpu family frvbf. */
--- 76,226 ----
, FRVBF_INSN_NLDSHI, FRVBF_INSN_NLDUHI, FRVBF_INSN_NLDI, FRVBF_INSN_NLDBFI
, FRVBF_INSN_NLDHFI, FRVBF_INSN_NLDFI, FRVBF_INSN_LDDI, FRVBF_INSN_LDDFI
, FRVBF_INSN_NLDDI, FRVBF_INSN_NLDDFI, FRVBF_INSN_LDQI, FRVBF_INSN_LDQFI
! , FRVBF_INSN_NLDQFI, FRVBF_INSN_STB, FRVBF_INSN_STH, FRVBF_INSN_ST
! , FRVBF_INSN_STBF, FRVBF_INSN_STHF, FRVBF_INSN_STF, FRVBF_INSN_STC
! , FRVBF_INSN_RSTB, FRVBF_INSN_RSTH, FRVBF_INSN_RST, FRVBF_INSN_RSTBF
! , FRVBF_INSN_RSTHF, FRVBF_INSN_RSTF, FRVBF_INSN_STD, FRVBF_INSN_STDF
! , FRVBF_INSN_STDC, FRVBF_INSN_RSTD, FRVBF_INSN_RSTDF, FRVBF_INSN_STQ
! , FRVBF_INSN_STQF, FRVBF_INSN_STQC, FRVBF_INSN_RSTQ, FRVBF_INSN_RSTQF
! , FRVBF_INSN_STBU, FRVBF_INSN_STHU, FRVBF_INSN_STU, FRVBF_INSN_STBFU
! , FRVBF_INSN_STHFU, FRVBF_INSN_STFU, FRVBF_INSN_STCU, FRVBF_INSN_STDU
! , FRVBF_INSN_STDFU, FRVBF_INSN_STDCU, FRVBF_INSN_STQU, FRVBF_INSN_STQFU
! , FRVBF_INSN_STQCU, FRVBF_INSN_CLDSB, FRVBF_INSN_CLDUB, FRVBF_INSN_CLDSH
! , FRVBF_INSN_CLDUH, FRVBF_INSN_CLD, FRVBF_INSN_CLDBF, FRVBF_INSN_CLDHF
! , FRVBF_INSN_CLDF, FRVBF_INSN_CLDD, FRVBF_INSN_CLDDF, FRVBF_INSN_CLDQ
! , FRVBF_INSN_CLDSBU, FRVBF_INSN_CLDUBU, FRVBF_INSN_CLDSHU, FRVBF_INSN_CLDUHU
! , FRVBF_INSN_CLDU, FRVBF_INSN_CLDBFU, FRVBF_INSN_CLDHFU, FRVBF_INSN_CLDFU
! , FRVBF_INSN_CLDDU, FRVBF_INSN_CLDDFU, FRVBF_INSN_CLDQU, FRVBF_INSN_CSTB
! , FRVBF_INSN_CSTH, FRVBF_INSN_CST, FRVBF_INSN_CSTBF, FRVBF_INSN_CSTHF
! , FRVBF_INSN_CSTF, FRVBF_INSN_CSTD, FRVBF_INSN_CSTDF, FRVBF_INSN_CSTQ
! , FRVBF_INSN_CSTBU, FRVBF_INSN_CSTHU, FRVBF_INSN_CSTU, FRVBF_INSN_CSTBFU
! , FRVBF_INSN_CSTHFU, FRVBF_INSN_CSTFU, FRVBF_INSN_CSTDU, FRVBF_INSN_CSTDFU
! , FRVBF_INSN_STBI, FRVBF_INSN_STHI, FRVBF_INSN_STI, FRVBF_INSN_STBFI
! , FRVBF_INSN_STHFI, FRVBF_INSN_STFI, FRVBF_INSN_STDI, FRVBF_INSN_STDFI
! , FRVBF_INSN_STQI, FRVBF_INSN_STQFI, FRVBF_INSN_SWAP, FRVBF_INSN_SWAPI
! , FRVBF_INSN_CSWAP, FRVBF_INSN_MOVGF, FRVBF_INSN_MOVFG, FRVBF_INSN_MOVGFD
! , FRVBF_INSN_MOVFGD, FRVBF_INSN_MOVGFQ, FRVBF_INSN_MOVFGQ, FRVBF_INSN_CMOVGF
! , FRVBF_INSN_CMOVFG, FRVBF_INSN_CMOVGFD, FRVBF_INSN_CMOVFGD, FRVBF_INSN_MOVGS
! , FRVBF_INSN_MOVSG, FRVBF_INSN_BRA, FRVBF_INSN_BNO, FRVBF_INSN_BEQ
! , FRVBF_INSN_BNE, FRVBF_INSN_BLE, FRVBF_INSN_BGT, FRVBF_INSN_BLT
! , FRVBF_INSN_BGE, FRVBF_INSN_BLS, FRVBF_INSN_BHI, FRVBF_INSN_BC
! , FRVBF_INSN_BNC, FRVBF_INSN_BN, FRVBF_INSN_BP, FRVBF_INSN_BV
! , FRVBF_INSN_BNV, FRVBF_INSN_FBRA, FRVBF_INSN_FBNO, FRVBF_INSN_FBNE
! , FRVBF_INSN_FBEQ, FRVBF_INSN_FBLG, FRVBF_INSN_FBUE, FRVBF_INSN_FBUL
! , FRVBF_INSN_FBGE, FRVBF_INSN_FBLT, FRVBF_INSN_FBUGE, FRVBF_INSN_FBUG
! , FRVBF_INSN_FBLE, FRVBF_INSN_FBGT, FRVBF_INSN_FBULE, FRVBF_INSN_FBU
! , FRVBF_INSN_FBO, FRVBF_INSN_BCTRLR, FRVBF_INSN_BRALR, FRVBF_INSN_BNOLR
! , FRVBF_INSN_BEQLR, FRVBF_INSN_BNELR, FRVBF_INSN_BLELR, FRVBF_INSN_BGTLR
! , FRVBF_INSN_BLTLR, FRVBF_INSN_BGELR, FRVBF_INSN_BLSLR, FRVBF_INSN_BHILR
! , FRVBF_INSN_BCLR, FRVBF_INSN_BNCLR, FRVBF_INSN_BNLR, FRVBF_INSN_BPLR
! , FRVBF_INSN_BVLR, FRVBF_INSN_BNVLR, FRVBF_INSN_FBRALR, FRVBF_INSN_FBNOLR
! , FRVBF_INSN_FBEQLR, FRVBF_INSN_FBNELR, FRVBF_INSN_FBLGLR, FRVBF_INSN_FBUELR
! , FRVBF_INSN_FBULLR, FRVBF_INSN_FBGELR, FRVBF_INSN_FBLTLR, FRVBF_INSN_FBUGELR
! , FRVBF_INSN_FBUGLR, FRVBF_INSN_FBLELR, FRVBF_INSN_FBGTLR, FRVBF_INSN_FBULELR
! , FRVBF_INSN_FBULR, FRVBF_INSN_FBOLR, FRVBF_INSN_BCRALR, FRVBF_INSN_BCNOLR
! , FRVBF_INSN_BCEQLR, FRVBF_INSN_BCNELR, FRVBF_INSN_BCLELR, FRVBF_INSN_BCGTLR
! , FRVBF_INSN_BCLTLR, FRVBF_INSN_BCGELR, FRVBF_INSN_BCLSLR, FRVBF_INSN_BCHILR
! , FRVBF_INSN_BCCLR, FRVBF_INSN_BCNCLR, FRVBF_INSN_BCNLR, FRVBF_INSN_BCPLR
! , FRVBF_INSN_BCVLR, FRVBF_INSN_BCNVLR, FRVBF_INSN_FCBRALR, FRVBF_INSN_FCBNOLR
! , FRVBF_INSN_FCBEQLR, FRVBF_INSN_FCBNELR, FRVBF_INSN_FCBLGLR, FRVBF_INSN_FCBUELR
! , FRVBF_INSN_FCBULLR, FRVBF_INSN_FCBGELR, FRVBF_INSN_FCBLTLR, FRVBF_INSN_FCBUGELR
! , FRVBF_INSN_FCBUGLR, FRVBF_INSN_FCBLELR, FRVBF_INSN_FCBGTLR, FRVBF_INSN_FCBULELR
! , FRVBF_INSN_FCBULR, FRVBF_INSN_FCBOLR, FRVBF_INSN_JMPL, FRVBF_INSN_CALLL
! , FRVBF_INSN_JMPIL, FRVBF_INSN_CALLIL, FRVBF_INSN_CALL, FRVBF_INSN_RETT
! , FRVBF_INSN_REI, FRVBF_INSN_TRA, FRVBF_INSN_TNO, FRVBF_INSN_TEQ
! , FRVBF_INSN_TNE, FRVBF_INSN_TLE, FRVBF_INSN_TGT, FRVBF_INSN_TLT
! , FRVBF_INSN_TGE, FRVBF_INSN_TLS, FRVBF_INSN_THI, FRVBF_INSN_TC
! , FRVBF_INSN_TNC, FRVBF_INSN_TN, FRVBF_INSN_TP, FRVBF_INSN_TV
! , FRVBF_INSN_TNV, FRVBF_INSN_FTRA, FRVBF_INSN_FTNO, FRVBF_INSN_FTNE
! , FRVBF_INSN_FTEQ, FRVBF_INSN_FTLG, FRVBF_INSN_FTUE, FRVBF_INSN_FTUL
! , FRVBF_INSN_FTGE, FRVBF_INSN_FTLT, FRVBF_INSN_FTUGE, FRVBF_INSN_FTUG
! , FRVBF_INSN_FTLE, FRVBF_INSN_FTGT, FRVBF_INSN_FTULE, FRVBF_INSN_FTU
! , FRVBF_INSN_FTO, FRVBF_INSN_TIRA, FRVBF_INSN_TINO, FRVBF_INSN_TIEQ
! , FRVBF_INSN_TINE, FRVBF_INSN_TILE, FRVBF_INSN_TIGT, FRVBF_INSN_TILT
! , FRVBF_INSN_TIGE, FRVBF_INSN_TILS, FRVBF_INSN_TIHI, FRVBF_INSN_TIC
! , FRVBF_INSN_TINC, FRVBF_INSN_TIN, FRVBF_INSN_TIP, FRVBF_INSN_TIV
! , FRVBF_INSN_TINV, FRVBF_INSN_FTIRA, FRVBF_INSN_FTINO, FRVBF_INSN_FTINE
! , FRVBF_INSN_FTIEQ, FRVBF_INSN_FTILG, FRVBF_INSN_FTIUE, FRVBF_INSN_FTIUL
! , FRVBF_INSN_FTIGE, FRVBF_INSN_FTILT, FRVBF_INSN_FTIUGE, FRVBF_INSN_FTIUG
! , FRVBF_INSN_FTILE, FRVBF_INSN_FTIGT, FRVBF_INSN_FTIULE, FRVBF_INSN_FTIU
! , FRVBF_INSN_FTIO, FRVBF_INSN_BREAK, FRVBF_INSN_MTRAP, FRVBF_INSN_ANDCR
! , FRVBF_INSN_ORCR, FRVBF_INSN_XORCR, FRVBF_INSN_NANDCR, FRVBF_INSN_NORCR
! , FRVBF_INSN_ANDNCR, FRVBF_INSN_ORNCR, FRVBF_INSN_NANDNCR, FRVBF_INSN_NORNCR
! , FRVBF_INSN_NOTCR, FRVBF_INSN_CKRA, FRVBF_INSN_CKNO, FRVBF_INSN_CKEQ
! , FRVBF_INSN_CKNE, FRVBF_INSN_CKLE, FRVBF_INSN_CKGT, FRVBF_INSN_CKLT
! , FRVBF_INSN_CKGE, FRVBF_INSN_CKLS, FRVBF_INSN_CKHI, FRVBF_INSN_CKC
! , FRVBF_INSN_CKNC, FRVBF_INSN_CKN, FRVBF_INSN_CKP, FRVBF_INSN_CKV
! , FRVBF_INSN_CKNV, FRVBF_INSN_FCKRA, FRVBF_INSN_FCKNO, FRVBF_INSN_FCKNE
! , FRVBF_INSN_FCKEQ, FRVBF_INSN_FCKLG, FRVBF_INSN_FCKUE, FRVBF_INSN_FCKUL
! , FRVBF_INSN_FCKGE, FRVBF_INSN_FCKLT, FRVBF_INSN_FCKUGE, FRVBF_INSN_FCKUG
! , FRVBF_INSN_FCKLE, FRVBF_INSN_FCKGT, FRVBF_INSN_FCKULE, FRVBF_INSN_FCKU
! , FRVBF_INSN_FCKO, FRVBF_INSN_CCKRA, FRVBF_INSN_CCKNO, FRVBF_INSN_CCKEQ
! , FRVBF_INSN_CCKNE, FRVBF_INSN_CCKLE, FRVBF_INSN_CCKGT, FRVBF_INSN_CCKLT
! , FRVBF_INSN_CCKGE, FRVBF_INSN_CCKLS, FRVBF_INSN_CCKHI, FRVBF_INSN_CCKC
! , FRVBF_INSN_CCKNC, FRVBF_INSN_CCKN, FRVBF_INSN_CCKP, FRVBF_INSN_CCKV
! , FRVBF_INSN_CCKNV, FRVBF_INSN_CFCKRA, FRVBF_INSN_CFCKNO, FRVBF_INSN_CFCKNE
! , FRVBF_INSN_CFCKEQ, FRVBF_INSN_CFCKLG, FRVBF_INSN_CFCKUE, FRVBF_INSN_CFCKUL
! , FRVBF_INSN_CFCKGE, FRVBF_INSN_CFCKLT, FRVBF_INSN_CFCKUGE, FRVBF_INSN_CFCKUG
! , FRVBF_INSN_CFCKLE, FRVBF_INSN_CFCKGT, FRVBF_INSN_CFCKULE, FRVBF_INSN_CFCKU
! , FRVBF_INSN_CFCKO, FRVBF_INSN_CJMPL, FRVBF_INSN_CCALLL, FRVBF_INSN_ICI
! , FRVBF_INSN_DCI, FRVBF_INSN_ICEI, FRVBF_INSN_DCEI, FRVBF_INSN_DCF
! , FRVBF_INSN_DCEF, FRVBF_INSN_WITLB, FRVBF_INSN_WDTLB, FRVBF_INSN_ITLBI
! , FRVBF_INSN_DTLBI, FRVBF_INSN_ICPL, FRVBF_INSN_DCPL, FRVBF_INSN_ICUL
! , FRVBF_INSN_DCUL, FRVBF_INSN_BAR, FRVBF_INSN_MEMBAR, FRVBF_INSN_COP1
! , FRVBF_INSN_COP2, FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR, FRVBF_INSN_CLRGA
! , FRVBF_INSN_CLRFA, FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR, FRVBF_INSN_COMMITGA
! , FRVBF_INSN_COMMITFA, FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI, FRVBF_INSN_FITOD
! , FRVBF_INSN_FDTOI, FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI, FRVBF_INSN_NFDITOS
! , FRVBF_INSN_NFDSTOI, FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI, FRVBF_INSN_NFITOS
! , FRVBF_INSN_NFSTOI, FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD, FRVBF_INSN_FDMOVS
! , FRVBF_INSN_CFMOVS, FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD, FRVBF_INSN_FDNEGS
! , FRVBF_INSN_CFNEGS, FRVBF_INSN_FABSS, FRVBF_INSN_FABSD, FRVBF_INSN_FDABSS
! , FRVBF_INSN_CFABSS, FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS, FRVBF_INSN_NFDSQRTS
! , FRVBF_INSN_FSQRTD, FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS, FRVBF_INSN_FADDS
! , FRVBF_INSN_FSUBS, FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS, FRVBF_INSN_FADDD
! , FRVBF_INSN_FSUBD, FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD, FRVBF_INSN_CFADDS
! , FRVBF_INSN_CFSUBS, FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS, FRVBF_INSN_NFADDS
! , FRVBF_INSN_NFSUBS, FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS, FRVBF_INSN_FCMPS
! , FRVBF_INSN_FCMPD, FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS, FRVBF_INSN_FMADDS
! , FRVBF_INSN_FMSUBS, FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD, FRVBF_INSN_FDMADDS
! , FRVBF_INSN_NFDMADDS, FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS, FRVBF_INSN_NFMADDS
! , FRVBF_INSN_NFMSUBS, FRVBF_INSN_FMAS, FRVBF_INSN_FMSS, FRVBF_INSN_FDMAS
! , FRVBF_INSN_FDMSS, FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS, FRVBF_INSN_CFMAS
! , FRVBF_INSN_CFMSS, FRVBF_INSN_FMAD, FRVBF_INSN_FMSD, FRVBF_INSN_NFMAS
! , FRVBF_INSN_NFMSS, FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS, FRVBF_INSN_FDMULS
! , FRVBF_INSN_FDDIVS, FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS, FRVBF_INSN_NFDMULCS
! , FRVBF_INSN_NFDADDS, FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS, FRVBF_INSN_NFDDIVS
! , FRVBF_INSN_NFDSADS, FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS, FRVBF_INSN_MHSETHIS
! , FRVBF_INSN_MHDSETS, FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH, FRVBF_INSN_MHDSETH
! , FRVBF_INSN_MAND, FRVBF_INSN_MOR, FRVBF_INSN_MXOR, FRVBF_INSN_CMAND
! , FRVBF_INSN_CMOR, FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT, FRVBF_INSN_CMNOT
! , FRVBF_INSN_MROTLI, FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT, FRVBF_INSN_MWCUTI
! , FRVBF_INSN_MCUT, FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS, FRVBF_INSN_MCUTSSI
! , FRVBF_INSN_MDCUTSSI, FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI, FRVBF_INSN_MSRLHI
! , FRVBF_INSN_MSRAHI, FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI, FRVBF_INSN_MCPLI
! , FRVBF_INSN_MSATHS, FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU, FRVBF_INSN_MCMPSH
! , FRVBF_INSN_MCMPUH, FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS, FRVBF_INSN_MADDHUS
! , FRVBF_INSN_MSUBHSS, FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS, FRVBF_INSN_CMADDHUS
! , FRVBF_INSN_CMSUBHSS, FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS, FRVBF_INSN_MQADDHUS
! , FRVBF_INSN_MQSUBHSS, FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS, FRVBF_INSN_CMQADDHUS
! , FRVBF_INSN_CMQSUBHSS, FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MADDACCS, FRVBF_INSN_MSUBACCS
! , FRVBF_INSN_MDADDACCS, FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS, FRVBF_INSN_MDASACCS
! , FRVBF_INSN_MMULHS, FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS, FRVBF_INSN_MMULXHU
! , FRVBF_INSN_CMMULHS, FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS, FRVBF_INSN_MQMULHU
! , FRVBF_INSN_MQMULXHS, FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS, FRVBF_INSN_CMQMULHU
! , FRVBF_INSN_MMACHS, FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS, FRVBF_INSN_MMRDHU
! , FRVBF_INSN_CMMACHS, FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS, FRVBF_INSN_MQMACHU
! , FRVBF_INSN_CMQMACHS, FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS, FRVBF_INSN_MQXMACXHS
! , FRVBF_INSN_MQMACXHS, FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU, FRVBF_INSN_MCPXIS
! , FRVBF_INSN_MCPXIU, FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU, FRVBF_INSN_CMCPXIS
! , FRVBF_INSN_CMCPXIU, FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU, FRVBF_INSN_MQCPXIS
! , FRVBF_INSN_MQCPXIU, FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW, FRVBF_INSN_MEXPDHD
! , FRVBF_INSN_CMEXPDHD, FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH, FRVBF_INSN_MUNPACKH
! , FRVBF_INSN_MDUNPACKH, FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH, FRVBF_INSN_MHTOB
! , FRVBF_INSN_CMHTOB, FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE, FRVBF_INSN_MNOP
! , FRVBF_INSN_MCLRACC_0, FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC, FRVBF_INSN_MRDACCG
! , FRVBF_INSN_MWTACC, FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1, FRVBF_INSN_MCOP2
! , FRVBF_INSN_FNOP, FRVBF_INSN__MAX
} FRVBF_INSN_TYPE;
/* Enum declaration for semantic formats in cpu family frvbf. */
*************** typedef enum frvbf_sfmt_type {
*** 241,301 ****
, FRVBF_SFMT_NLDQU, FRVBF_SFMT_LDQFU, FRVBF_SFMT_LDQCU, FRVBF_SFMT_NLDQFU
, FRVBF_SFMT_LDSBI, FRVBF_SFMT_LDBFI, FRVBF_SFMT_NLDSBI, FRVBF_SFMT_NLDBFI
, FRVBF_SFMT_LDDI, FRVBF_SFMT_LDDFI, FRVBF_SFMT_NLDDI, FRVBF_SFMT_NLDDFI
! , FRVBF_SFMT_LDQI, FRVBF_SFMT_LDQFI, FRVBF_SFMT_NLDQI, FRVBF_SFMT_NLDQFI
! , FRVBF_SFMT_STB, FRVBF_SFMT_STBF, FRVBF_SFMT_STC, FRVBF_SFMT_RSTB
! , FRVBF_SFMT_RSTBF, FRVBF_SFMT_STD, FRVBF_SFMT_STDF, FRVBF_SFMT_STDC
! , FRVBF_SFMT_RSTD, FRVBF_SFMT_RSTDF, FRVBF_SFMT_STBU, FRVBF_SFMT_STBFU
! , FRVBF_SFMT_STCU, FRVBF_SFMT_STDU, FRVBF_SFMT_STDFU, FRVBF_SFMT_STDCU
! , FRVBF_SFMT_STQU, FRVBF_SFMT_CLDSB, FRVBF_SFMT_CLDBF, FRVBF_SFMT_CLDD
! , FRVBF_SFMT_CLDDF, FRVBF_SFMT_CLDQ, FRVBF_SFMT_CLDSBU, FRVBF_SFMT_CLDBFU
! , FRVBF_SFMT_CLDDU, FRVBF_SFMT_CLDDFU, FRVBF_SFMT_CLDQU, FRVBF_SFMT_CSTB
! , FRVBF_SFMT_CSTBF, FRVBF_SFMT_CSTD, FRVBF_SFMT_CSTDF, FRVBF_SFMT_CSTBU
! , FRVBF_SFMT_CSTBFU, FRVBF_SFMT_CSTDU, FRVBF_SFMT_CSTDFU, FRVBF_SFMT_STBI
! , FRVBF_SFMT_STBFI, FRVBF_SFMT_STDI, FRVBF_SFMT_STDFI, FRVBF_SFMT_SWAP
! , FRVBF_SFMT_SWAPI, FRVBF_SFMT_CSWAP, FRVBF_SFMT_MOVGF, FRVBF_SFMT_MOVFG
! , FRVBF_SFMT_MOVGFD, FRVBF_SFMT_MOVFGD, FRVBF_SFMT_MOVGFQ, FRVBF_SFMT_MOVFGQ
! , FRVBF_SFMT_CMOVGF, FRVBF_SFMT_CMOVFG, FRVBF_SFMT_CMOVGFD, FRVBF_SFMT_CMOVFGD
! , FRVBF_SFMT_MOVGS, FRVBF_SFMT_MOVSG, FRVBF_SFMT_BRA, FRVBF_SFMT_BNO
! , FRVBF_SFMT_BEQ, FRVBF_SFMT_FBNE, FRVBF_SFMT_BCTRLR, FRVBF_SFMT_BRALR
! , FRVBF_SFMT_BNOLR, FRVBF_SFMT_BEQLR, FRVBF_SFMT_FBEQLR, FRVBF_SFMT_BCRALR
! , FRVBF_SFMT_BCNOLR, FRVBF_SFMT_BCEQLR, FRVBF_SFMT_FCBEQLR, FRVBF_SFMT_JMPL
! , FRVBF_SFMT_JMPIL, FRVBF_SFMT_CALL, FRVBF_SFMT_RETT, FRVBF_SFMT_REI
! , FRVBF_SFMT_TRA, FRVBF_SFMT_TEQ, FRVBF_SFMT_FTNE, FRVBF_SFMT_TIRA
! , FRVBF_SFMT_TIEQ, FRVBF_SFMT_FTINE, FRVBF_SFMT_BREAK, FRVBF_SFMT_ANDCR
! , FRVBF_SFMT_NOTCR, FRVBF_SFMT_CKRA, FRVBF_SFMT_CKEQ, FRVBF_SFMT_FCKRA
! , FRVBF_SFMT_FCKNE, FRVBF_SFMT_CCKRA, FRVBF_SFMT_CCKEQ, FRVBF_SFMT_CFCKRA
! , FRVBF_SFMT_CFCKNE, FRVBF_SFMT_CJMPL, FRVBF_SFMT_ICI, FRVBF_SFMT_ICEI
! , FRVBF_SFMT_ICPL, FRVBF_SFMT_ICUL, FRVBF_SFMT_CLRGR, FRVBF_SFMT_CLRFR
! , FRVBF_SFMT_COMMITGR, FRVBF_SFMT_COMMITFR, FRVBF_SFMT_FITOS, FRVBF_SFMT_FSTOI
! , FRVBF_SFMT_FITOD, FRVBF_SFMT_FDTOI, FRVBF_SFMT_FDITOS, FRVBF_SFMT_FDSTOI
! , FRVBF_SFMT_CFITOS, FRVBF_SFMT_CFSTOI, FRVBF_SFMT_NFITOS, FRVBF_SFMT_NFSTOI
! , FRVBF_SFMT_FMOVS, FRVBF_SFMT_FMOVD, FRVBF_SFMT_FDMOVS, FRVBF_SFMT_CFMOVS
! , FRVBF_SFMT_NFSQRTS, FRVBF_SFMT_FADDS, FRVBF_SFMT_FADDD, FRVBF_SFMT_CFADDS
! , FRVBF_SFMT_NFADDS, FRVBF_SFMT_FCMPS, FRVBF_SFMT_FCMPD, FRVBF_SFMT_CFCMPS
! , FRVBF_SFMT_FDCMPS, FRVBF_SFMT_FMADDS, FRVBF_SFMT_FMADDD, FRVBF_SFMT_FDMADDS
! , FRVBF_SFMT_CFMADDS, FRVBF_SFMT_NFMADDS, FRVBF_SFMT_FMAS, FRVBF_SFMT_FDMAS
! , FRVBF_SFMT_CFMAS, FRVBF_SFMT_NFDCMPS, FRVBF_SFMT_MHSETLOS, FRVBF_SFMT_MHSETHIS
! , FRVBF_SFMT_MHDSETS, FRVBF_SFMT_MHSETLOH, FRVBF_SFMT_MHSETHIH, FRVBF_SFMT_MHDSETH
! , FRVBF_SFMT_MAND, FRVBF_SFMT_CMAND, FRVBF_SFMT_MNOT, FRVBF_SFMT_CMNOT
! , FRVBF_SFMT_MROTLI, FRVBF_SFMT_MWCUT, FRVBF_SFMT_MWCUTI, FRVBF_SFMT_MCUT
! , FRVBF_SFMT_MCUTI, FRVBF_SFMT_MDCUTSSI, FRVBF_SFMT_MSLLHI, FRVBF_SFMT_MDROTLI
! , FRVBF_SFMT_MCPLHI, FRVBF_SFMT_MCPLI, FRVBF_SFMT_MSATHS, FRVBF_SFMT_MQSATHS
! , FRVBF_SFMT_MCMPSH, FRVBF_SFMT_MABSHS, FRVBF_SFMT_CMADDHSS, FRVBF_SFMT_CMQADDHSS
! , FRVBF_SFMT_MADDACCS, FRVBF_SFMT_MDADDACCS, FRVBF_SFMT_MASACCS, FRVBF_SFMT_MDASACCS
! , FRVBF_SFMT_MMULHS, FRVBF_SFMT_CMMULHS, FRVBF_SFMT_MQMULHS, FRVBF_SFMT_CMQMULHS
! , FRVBF_SFMT_MMACHS, FRVBF_SFMT_MMACHU, FRVBF_SFMT_CMMACHS, FRVBF_SFMT_CMMACHU
! , FRVBF_SFMT_MQMACHS, FRVBF_SFMT_MQMACHU, FRVBF_SFMT_CMQMACHS, FRVBF_SFMT_CMQMACHU
! , FRVBF_SFMT_MCPXRS, FRVBF_SFMT_CMCPXRS, FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW
! , FRVBF_SFMT_CMEXPDHW, FRVBF_SFMT_MEXPDHD, FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH
! , FRVBF_SFMT_MDPACKH, FRVBF_SFMT_MUNPACKH, FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH
! , FRVBF_SFMT_CMBTOH, FRVBF_SFMT_MHTOB, FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE
! , FRVBF_SFMT_CMBTOHE, FRVBF_SFMT_MCLRACC_0, FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG
! , FRVBF_SFMT_MWTACC, FRVBF_SFMT_MWTACCG
} FRVBF_SFMT_TYPE;
/* Function unit handlers (user written). */
extern int frvbf_model_frv_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int frvbf_model_fr500_u_dcul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
extern int frvbf_model_fr500_u_icul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
extern int frvbf_model_fr500_u_dcpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
--- 241,302 ----
, FRVBF_SFMT_NLDQU, FRVBF_SFMT_LDQFU, FRVBF_SFMT_LDQCU, FRVBF_SFMT_NLDQFU
, FRVBF_SFMT_LDSBI, FRVBF_SFMT_LDBFI, FRVBF_SFMT_NLDSBI, FRVBF_SFMT_NLDBFI
, FRVBF_SFMT_LDDI, FRVBF_SFMT_LDDFI, FRVBF_SFMT_NLDDI, FRVBF_SFMT_NLDDFI
! , FRVBF_SFMT_LDQI, FRVBF_SFMT_LDQFI, FRVBF_SFMT_NLDQFI, FRVBF_SFMT_STB
! , FRVBF_SFMT_STBF, FRVBF_SFMT_STC, FRVBF_SFMT_RSTB, FRVBF_SFMT_RSTBF
! , FRVBF_SFMT_STD, FRVBF_SFMT_STDF, FRVBF_SFMT_STDC, FRVBF_SFMT_RSTD
! , FRVBF_SFMT_RSTDF, FRVBF_SFMT_STBU, FRVBF_SFMT_STBFU, FRVBF_SFMT_STCU
! , FRVBF_SFMT_STDU, FRVBF_SFMT_STDFU, FRVBF_SFMT_STDCU, FRVBF_SFMT_STQU
! , FRVBF_SFMT_CLDSB, FRVBF_SFMT_CLDBF, FRVBF_SFMT_CLDD, FRVBF_SFMT_CLDDF
! , FRVBF_SFMT_CLDQ, FRVBF_SFMT_CLDSBU, FRVBF_SFMT_CLDBFU, FRVBF_SFMT_CLDDU
! , FRVBF_SFMT_CLDDFU, FRVBF_SFMT_CLDQU, FRVBF_SFMT_CSTB, FRVBF_SFMT_CSTBF
! , FRVBF_SFMT_CSTD, FRVBF_SFMT_CSTDF, FRVBF_SFMT_CSTBU, FRVBF_SFMT_CSTBFU
! , FRVBF_SFMT_CSTDU, FRVBF_SFMT_CSTDFU, FRVBF_SFMT_STBI, FRVBF_SFMT_STBFI
! , FRVBF_SFMT_STDI, FRVBF_SFMT_STDFI, FRVBF_SFMT_SWAP, FRVBF_SFMT_SWAPI
! , FRVBF_SFMT_CSWAP, FRVBF_SFMT_MOVGF, FRVBF_SFMT_MOVFG, FRVBF_SFMT_MOVGFD
! , FRVBF_SFMT_MOVFGD, FRVBF_SFMT_MOVGFQ, FRVBF_SFMT_MOVFGQ, FRVBF_SFMT_CMOVGF
! , FRVBF_SFMT_CMOVFG, FRVBF_SFMT_CMOVGFD, FRVBF_SFMT_CMOVFGD, FRVBF_SFMT_MOVGS
! , FRVBF_SFMT_MOVSG, FRVBF_SFMT_BRA, FRVBF_SFMT_BNO, FRVBF_SFMT_BEQ
! , FRVBF_SFMT_FBNE, FRVBF_SFMT_BCTRLR, FRVBF_SFMT_BRALR, FRVBF_SFMT_BNOLR
! , FRVBF_SFMT_BEQLR, FRVBF_SFMT_FBEQLR, FRVBF_SFMT_BCRALR, FRVBF_SFMT_BCNOLR
! , FRVBF_SFMT_BCEQLR, FRVBF_SFMT_FCBEQLR, FRVBF_SFMT_JMPL, FRVBF_SFMT_JMPIL
! , FRVBF_SFMT_CALL, FRVBF_SFMT_RETT, FRVBF_SFMT_REI, FRVBF_SFMT_TRA
! , FRVBF_SFMT_TEQ, FRVBF_SFMT_FTNE, FRVBF_SFMT_TIRA, FRVBF_SFMT_TIEQ
! , FRVBF_SFMT_FTINE, FRVBF_SFMT_BREAK, FRVBF_SFMT_ANDCR, FRVBF_SFMT_NOTCR
! , FRVBF_SFMT_CKRA, FRVBF_SFMT_CKEQ, FRVBF_SFMT_FCKRA, FRVBF_SFMT_FCKNE
! , FRVBF_SFMT_CCKRA, FRVBF_SFMT_CCKEQ, FRVBF_SFMT_CFCKRA, FRVBF_SFMT_CFCKNE
! , FRVBF_SFMT_CJMPL, FRVBF_SFMT_ICI, FRVBF_SFMT_ICEI, FRVBF_SFMT_ICPL
! , FRVBF_SFMT_ICUL, FRVBF_SFMT_CLRGR, FRVBF_SFMT_CLRFR, FRVBF_SFMT_COMMITGR
! , FRVBF_SFMT_COMMITFR, FRVBF_SFMT_FITOS, FRVBF_SFMT_FSTOI, FRVBF_SFMT_FITOD
! , FRVBF_SFMT_FDTOI, FRVBF_SFMT_FDITOS, FRVBF_SFMT_FDSTOI, FRVBF_SFMT_CFITOS
! , FRVBF_SFMT_CFSTOI, FRVBF_SFMT_NFITOS, FRVBF_SFMT_NFSTOI, FRVBF_SFMT_FMOVS
! , FRVBF_SFMT_FMOVD, FRVBF_SFMT_FDMOVS, FRVBF_SFMT_CFMOVS, FRVBF_SFMT_NFSQRTS
! , FRVBF_SFMT_FADDS, FRVBF_SFMT_FADDD, FRVBF_SFMT_CFADDS, FRVBF_SFMT_NFADDS
! , FRVBF_SFMT_FCMPS, FRVBF_SFMT_FCMPD, FRVBF_SFMT_CFCMPS, FRVBF_SFMT_FDCMPS
! , FRVBF_SFMT_FMADDS, FRVBF_SFMT_FMADDD, FRVBF_SFMT_FDMADDS, FRVBF_SFMT_CFMADDS
! , FRVBF_SFMT_NFMADDS, FRVBF_SFMT_FMAS, FRVBF_SFMT_FDMAS, FRVBF_SFMT_CFMAS
! , FRVBF_SFMT_NFDCMPS, FRVBF_SFMT_MHSETLOS, FRVBF_SFMT_MHSETHIS, FRVBF_SFMT_MHDSETS
! , FRVBF_SFMT_MHSETLOH, FRVBF_SFMT_MHSETHIH, FRVBF_SFMT_MHDSETH, FRVBF_SFMT_MAND
! , FRVBF_SFMT_CMAND, FRVBF_SFMT_MNOT, FRVBF_SFMT_CMNOT, FRVBF_SFMT_MROTLI
! , FRVBF_SFMT_MWCUT, FRVBF_SFMT_MWCUTI, FRVBF_SFMT_MCUT, FRVBF_SFMT_MCUTI
! , FRVBF_SFMT_MDCUTSSI, FRVBF_SFMT_MSLLHI, FRVBF_SFMT_MDROTLI, FRVBF_SFMT_MCPLHI
! , FRVBF_SFMT_MCPLI, FRVBF_SFMT_MSATHS, FRVBF_SFMT_MQSATHS, FRVBF_SFMT_MCMPSH
! , FRVBF_SFMT_MABSHS, FRVBF_SFMT_CMADDHSS, FRVBF_SFMT_CMQADDHSS, FRVBF_SFMT_MADDACCS
! , FRVBF_SFMT_MDADDACCS, FRVBF_SFMT_MASACCS, FRVBF_SFMT_MDASACCS, FRVBF_SFMT_MMULHS
! , FRVBF_SFMT_CMMULHS, FRVBF_SFMT_MQMULHS, FRVBF_SFMT_CMQMULHS, FRVBF_SFMT_MMACHS
! , FRVBF_SFMT_MMACHU, FRVBF_SFMT_CMMACHS, FRVBF_SFMT_CMMACHU, FRVBF_SFMT_MQMACHS
! , FRVBF_SFMT_MQMACHU, FRVBF_SFMT_CMQMACHS, FRVBF_SFMT_CMQMACHU, FRVBF_SFMT_MCPXRS
! , FRVBF_SFMT_CMCPXRS, FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW, FRVBF_SFMT_CMEXPDHW
! , FRVBF_SFMT_MEXPDHD, FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH, FRVBF_SFMT_MDPACKH
! , FRVBF_SFMT_MUNPACKH, FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH, FRVBF_SFMT_CMBTOH
! , FRVBF_SFMT_MHTOB, FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE, FRVBF_SFMT_CMBTOHE
! , FRVBF_SFMT_MCLRACC_0, FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG, FRVBF_SFMT_MWTACC
! , FRVBF_SFMT_MWTACCG
} FRVBF_SFMT_TYPE;
/* Function unit handlers (user written). */
extern int frvbf_model_frv_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+ extern int frvbf_model_fr500_u_commit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRk*/, INT /*FRk*/);
extern int frvbf_model_fr500_u_dcul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
extern int frvbf_model_fr500_u_icul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
extern int frvbf_model_fr500_u_dcpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
Index: sim/frv/model.c
===================================================================
RCS file: /cvs/src/src/sim/frv/model.c,v
retrieving revision 1.3
diff -c -p -r1.3 model.c
*** sim/frv/model.c 12 Sep 2003 22:05:21 -0000 1.3
--- sim/frv/model.c 24 Sep 2003 18:52:22 -0000
*************** model_frv_ldqfi (SIM_CPU *current_cpu, v
*** 2627,2648 ****
}
static int
- model_frv_nldqi (SIM_CPU *current_cpu, void *sem_arg)
- {
- #define FLD(f) abuf->fields.sfmt_stdi.f
- const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
- const IDESC * UNUSED idesc = abuf->idesc;
- int cycles = 0;
- {
- int referenced = 0;
- int UNUSED insn_referenced = abuf->written;
- cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
- }
- return cycles;
- #undef FLD
- }
-
- static int
model_frv_nldqfi (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_stdfi.f
--- 2627,2632 ----
*************** model_fr500_ldqfi (SIM_CPU *current_cpu,
*** 15913,15940 ****
}
static int
- model_fr500_nldqi (SIM_CPU *current_cpu, void *sem_arg)
- {
- #define FLD(f) abuf->fields.sfmt_stdi.f
- const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
- const IDESC * UNUSED idesc = abuf->idesc;
- int cycles = 0;
- {
- int referenced = 0;
- int UNUSED insn_referenced = abuf->written;
- INT in_GRi = -1;
- INT in_GRj = -1;
- INT out_GRk = -1;
- INT out_GRdoublek = -1;
- in_GRi = FLD (in_GRi);
- if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
- cycles += frvbf_model_fr500_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
- }
- return cycles;
- #undef FLD
- }
-
- static int
model_fr500_nldqfi (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_stdfi.f
--- 15897,15902 ----
*************** model_fr500_commitgr (SIM_CPU *current_c
*** 24215,24221 ****
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
! cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
--- 24177,24185 ----
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
! INT in_GRk = -1;
! INT in_FRk = -1;
! cycles += frvbf_model_fr500_u_commit (current_cpu, idesc, 0, referenced, in_GRk, in_FRk);
}
return cycles;
#undef FLD
*************** model_fr500_commitfr (SIM_CPU *current_c
*** 24231,24237 ****
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
! cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
--- 24195,24203 ----
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
! INT in_GRk = -1;
! INT in_FRk = -1;
! cycles += frvbf_model_fr500_u_commit (current_cpu, idesc, 0, referenced, in_GRk, in_FRk);
}
return cycles;
#undef FLD
*************** model_fr500_commitga (SIM_CPU *current_c
*** 24247,24253 ****
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
! cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
--- 24213,24221 ----
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
! INT in_GRk = -1;
! INT in_FRk = -1;
! cycles += frvbf_model_fr500_u_commit (current_cpu, idesc, 0, referenced, in_GRk, in_FRk);
}
return cycles;
#undef FLD
*************** model_fr500_commitfa (SIM_CPU *current_c
*** 24263,24269 ****
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
! cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
--- 24231,24239 ----
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
! INT in_GRk = -1;
! INT in_FRk = -1;
! cycles += frvbf_model_fr500_u_commit (current_cpu, idesc, 0, referenced, in_GRk, in_FRk);
}
return cycles;
#undef FLD
*************** model_fr500_cfdivs (SIM_CPU *current_cpu
*** 25316,25332 ****
int UNUSED insn_referenced = abuf->written;
INT in_FRi = -1;
INT in_FRj = -1;
- INT in_FRdoublei = -1;
- INT in_FRdoublej = -1;
INT out_FRk = -1;
- INT out_FRdoublek = -1;
in_FRi = FLD (in_FRi);
in_FRj = FLD (in_FRj);
out_FRk = FLD (out_FRk);
if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
! if (insn_referenced & (1 << 4)) referenced |= 1 << 4;
! cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
}
return cycles;
#undef FLD
--- 25286,25299 ----
int UNUSED insn_referenced = abuf->written;
INT in_FRi = -1;
INT in_FRj = -1;
INT out_FRk = -1;
in_FRi = FLD (in_FRi);
in_FRj = FLD (in_FRj);
out_FRk = FLD (out_FRk);
if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
! if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
! cycles += frvbf_model_fr500_u_float_div (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, out_FRk);
}
return cycles;
#undef FLD
*************** model_fr500_nfdivs (SIM_CPU *current_cpu
*** 25428,25444 ****
int UNUSED insn_referenced = abuf->written;
INT in_FRi = -1;
INT in_FRj = -1;
- INT in_FRdoublei = -1;
- INT in_FRdoublej = -1;
INT out_FRk = -1;
- INT out_FRdoublek = -1;
in_FRi = FLD (in_FRi);
in_FRj = FLD (in_FRj);
out_FRk = FLD (out_FRk);
referenced |= 1 << 0;
referenced |= 1 << 1;
! referenced |= 1 << 4;
! cycles += frvbf_model_fr500_u_float_arith (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, in_FRdoublei, in_FRdoublej, out_FRk, out_FRdoublek);
}
return cycles;
#undef FLD
--- 25395,25408 ----
int UNUSED insn_referenced = abuf->written;
INT in_FRi = -1;
INT in_FRj = -1;
INT out_FRk = -1;
in_FRi = FLD (in_FRi);
in_FRj = FLD (in_FRj);
out_FRk = FLD (out_FRk);
referenced |= 1 << 0;
referenced |= 1 << 1;
! referenced |= 1 << 2;
! cycles += frvbf_model_fr500_u_float_div (current_cpu, idesc, 0, referenced, in_FRi, in_FRj, out_FRk);
}
return cycles;
#undef FLD
*************** model_tomcat_ldqfi (SIM_CPU *current_cpu
*** 31870,31891 ****
}
static int
- model_tomcat_nldqi (SIM_CPU *current_cpu, void *sem_arg)
- {
- #define FLD(f) abuf->fields.sfmt_stdi.f
- const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
- const IDESC * UNUSED idesc = abuf->idesc;
- int cycles = 0;
- {
- int referenced = 0;
- int UNUSED insn_referenced = abuf->written;
- cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
- }
- return cycles;
- #undef FLD
- }
-
- static int
model_tomcat_nldqfi (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_stdfi.f
--- 31834,31839 ----
*************** model_fr400_ldqfi (SIM_CPU *current_cpu,
*** 44820,44841 ****
}
static int
- model_fr400_nldqi (SIM_CPU *current_cpu, void *sem_arg)
- {
- #define FLD(f) abuf->fields.sfmt_stdi.f
- const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
- const IDESC * UNUSED idesc = abuf->idesc;
- int cycles = 0;
- {
- int referenced = 0;
- int UNUSED insn_referenced = abuf->written;
- cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
- }
- return cycles;
- #undef FLD
- }
-
- static int
model_fr400_nldqfi (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_stdfi.f
--- 44768,44773 ----
*************** model_simple_ldqfi (SIM_CPU *current_cpu
*** 59685,59706 ****
}
static int
- model_simple_nldqi (SIM_CPU *current_cpu, void *sem_arg)
- {
- #define FLD(f) abuf->fields.sfmt_stdi.f
- const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
- const IDESC * UNUSED idesc = abuf->idesc;
- int cycles = 0;
- {
- int referenced = 0;
- int UNUSED insn_referenced = abuf->written;
- cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
- }
- return cycles;
- #undef FLD
- }
-
- static int
model_simple_nldqfi (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_stdfi.f
--- 59617,59622 ----
*************** static const INSN_TIMING frv_timing[] =
*** 69106,69112 ****
{ FRVBF_INSN_NLDDFI, model_frv_nlddfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_LDQI, model_frv_ldqi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_LDQFI, model_frv_ldqfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
- { FRVBF_INSN_NLDQI, model_frv_nldqi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_NLDQFI, model_frv_nldqfi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_STB, model_frv_stb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_STH, model_frv_sth, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
--- 69022,69027 ----
*************** static const INSN_TIMING fr500_timing[]
*** 69857,69863 ****
{ FRVBF_INSN_NLDDFI, model_fr500_nlddfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
{ FRVBF_INSN_LDQI, model_fr500_ldqi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
{ FRVBF_INSN_LDQFI, model_fr500_ldqfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
- { FRVBF_INSN_NLDQI, model_fr500_nldqi, { { (int) UNIT_FR500_U_GR_LOAD, 1, 1 } } },
{ FRVBF_INSN_NLDQFI, model_fr500_nldqfi, { { (int) UNIT_FR500_U_FR_LOAD, 1, 1 } } },
{ FRVBF_INSN_STB, model_fr500_stb, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
{ FRVBF_INSN_STH, model_fr500_sth, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } },
--- 69772,69777 ----
*************** static const INSN_TIMING fr500_timing[]
*** 70227,70236 ****
{ FRVBF_INSN_CLRFR, model_fr500_clrfr, { { (int) UNIT_FR500_U_CLRFR, 1, 1 } } },
{ FRVBF_INSN_CLRGA, model_fr500_clrga, { { (int) UNIT_FR500_U_CLRGR, 1, 1 } } },
{ FRVBF_INSN_CLRFA, model_fr500_clrfa, { { (int) UNIT_FR500_U_CLRFR, 1, 1 } } },
! { FRVBF_INSN_COMMITGR, model_fr500_commitgr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
! { FRVBF_INSN_COMMITFR, model_fr500_commitfr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
! { FRVBF_INSN_COMMITGA, model_fr500_commitga, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
! { FRVBF_INSN_COMMITFA, model_fr500_commitfa, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_FITOS, model_fr500_fitos, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } },
{ FRVBF_INSN_FSTOI, model_fr500_fstoi, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } },
{ FRVBF_INSN_FITOD, model_fr500_fitod, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } },
--- 70141,70150 ----
{ FRVBF_INSN_CLRFR, model_fr500_clrfr, { { (int) UNIT_FR500_U_CLRFR, 1, 1 } } },
{ FRVBF_INSN_CLRGA, model_fr500_clrga, { { (int) UNIT_FR500_U_CLRGR, 1, 1 } } },
{ FRVBF_INSN_CLRFA, model_fr500_clrfa, { { (int) UNIT_FR500_U_CLRFR, 1, 1 } } },
! { FRVBF_INSN_COMMITGR, model_fr500_commitgr, { { (int) UNIT_FR500_U_COMMIT, 1, 1 } } },
! { FRVBF_INSN_COMMITFR, model_fr500_commitfr, { { (int) UNIT_FR500_U_COMMIT, 1, 1 } } },
! { FRVBF_INSN_COMMITGA, model_fr500_commitga, { { (int) UNIT_FR500_U_COMMIT, 1, 1 } } },
! { FRVBF_INSN_COMMITFA, model_fr500_commitfa, { { (int) UNIT_FR500_U_COMMIT, 1, 1 } } },
{ FRVBF_INSN_FITOS, model_fr500_fitos, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } },
{ FRVBF_INSN_FSTOI, model_fr500_fstoi, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } },
{ FRVBF_INSN_FITOD, model_fr500_fitod, { { (int) UNIT_FR500_U_FLOAT_CONVERT, 1, 1 } } },
*************** static const INSN_TIMING fr500_timing[]
*** 70272,70282 ****
{ FRVBF_INSN_CFADDS, model_fr500_cfadds, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
{ FRVBF_INSN_CFSUBS, model_fr500_cfsubs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
{ FRVBF_INSN_CFMULS, model_fr500_cfmuls, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
! { FRVBF_INSN_CFDIVS, model_fr500_cfdivs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
{ FRVBF_INSN_NFADDS, model_fr500_nfadds, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
{ FRVBF_INSN_NFSUBS, model_fr500_nfsubs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
{ FRVBF_INSN_NFMULS, model_fr500_nfmuls, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
! { FRVBF_INSN_NFDIVS, model_fr500_nfdivs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
{ FRVBF_INSN_FCMPS, model_fr500_fcmps, { { (int) UNIT_FR500_U_FLOAT_COMPARE, 1, 1 } } },
{ FRVBF_INSN_FCMPD, model_fr500_fcmpd, { { (int) UNIT_FR500_U_FLOAT_COMPARE, 1, 1 } } },
{ FRVBF_INSN_CFCMPS, model_fr500_cfcmps, { { (int) UNIT_FR500_U_FLOAT_COMPARE, 1, 1 } } },
--- 70186,70196 ----
{ FRVBF_INSN_CFADDS, model_fr500_cfadds, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
{ FRVBF_INSN_CFSUBS, model_fr500_cfsubs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
{ FRVBF_INSN_CFMULS, model_fr500_cfmuls, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
! { FRVBF_INSN_CFDIVS, model_fr500_cfdivs, { { (int) UNIT_FR500_U_FLOAT_DIV, 1, 1 } } },
{ FRVBF_INSN_NFADDS, model_fr500_nfadds, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
{ FRVBF_INSN_NFSUBS, model_fr500_nfsubs, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
{ FRVBF_INSN_NFMULS, model_fr500_nfmuls, { { (int) UNIT_FR500_U_FLOAT_ARITH, 1, 1 } } },
! { FRVBF_INSN_NFDIVS, model_fr500_nfdivs, { { (int) UNIT_FR500_U_FLOAT_DIV, 1, 1 } } },
{ FRVBF_INSN_FCMPS, model_fr500_fcmps, { { (int) UNIT_FR500_U_FLOAT_COMPARE, 1, 1 } } },
{ FRVBF_INSN_FCMPD, model_fr500_fcmpd, { { (int) UNIT_FR500_U_FLOAT_COMPARE, 1, 1 } } },
{ FRVBF_INSN_CFCMPS, model_fr500_cfcmps, { { (int) UNIT_FR500_U_FLOAT_COMPARE, 1, 1 } } },
*************** static const INSN_TIMING tomcat_timing[]
*** 70608,70614 ****
{ FRVBF_INSN_NLDDFI, model_tomcat_nlddfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_LDQI, model_tomcat_ldqi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_LDQFI, model_tomcat_ldqfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
- { FRVBF_INSN_NLDQI, model_tomcat_nldqi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_NLDQFI, model_tomcat_nldqfi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_STB, model_tomcat_stb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_STH, model_tomcat_sth, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
--- 70522,70527 ----
*************** static const INSN_TIMING fr400_timing[]
*** 71359,71365 ****
{ FRVBF_INSN_NLDDFI, model_fr400_nlddfi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_LDQI, model_fr400_ldqi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_LDQFI, model_fr400_ldqfi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
- { FRVBF_INSN_NLDQI, model_fr400_nldqi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_NLDQFI, model_fr400_nldqfi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_STB, model_fr400_stb, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
{ FRVBF_INSN_STH, model_fr400_sth, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } },
--- 71272,71277 ----
*************** static const INSN_TIMING simple_timing[]
*** 72110,72116 ****
{ FRVBF_INSN_NLDDFI, model_simple_nlddfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_LDQI, model_simple_ldqi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_LDQFI, model_simple_ldqfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
- { FRVBF_INSN_NLDQI, model_simple_nldqi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_NLDQFI, model_simple_nldqfi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_STB, model_simple_stb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_STH, model_simple_sth, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
--- 72022,72027 ----
Index: sim/frv/profile-fr400.c
===================================================================
RCS file: /cvs/src/src/sim/frv/profile-fr400.c,v
retrieving revision 1.1
diff -c -p -r1.1 profile-fr400.c
*** sim/frv/profile-fr400.c 29 Aug 2003 16:35:46 -0000 1.1
--- sim/frv/profile-fr400.c 24 Sep 2003 18:52:22 -0000
*************** frvbf_model_fr400_u_gr2spr (SIM_CPU *cpu
*** 621,675 ****
in_GRj, out_spr);
}
- /* Top up the post-processing time of the given FR by the given number of
- cycles. */
- static void
- update_FR_ptime (SIM_CPU *cpu, INT out_FR, int cycles)
- {
- if (out_FR >= 0)
- {
- FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
- /* If a load is pending on this register, then add the cycles to
- the post processing time for this register. Otherwise apply it
- directly to the latency of the register. */
- if (! load_pending_for_register (cpu, out_FR, 1, REGTYPE_FR))
- {
- int *fr = ps->fr_latency;
- fr[out_FR] += cycles;
- }
- else
- ps->fr_ptime[out_FR] += cycles;
- }
- }
-
- static void
- update_FRdouble_ptime (SIM_CPU *cpu, INT out_FR, int cycles)
- {
- if (out_FR >= 0)
- {
- FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
- /* If a load is pending on this register, then add the cycles to
- the post processing time for this register. Otherwise apply it
- directly to the latency of the register. */
- if (! load_pending_for_register (cpu, out_FR, 2, REGTYPE_FR))
- {
- int *fr = ps->fr_latency;
- fr[out_FR] += cycles;
- if (out_FR < 63)
- fr[out_FR + 1] += cycles;
- }
- else
- {
- /* On the fr400, loads are available to media insns one cycle early,
- so knock one cycle off the post processing time to account for
- this. */
- ps->fr_ptime[out_FR] += cycles - 1;
- if (out_FR < 63)
- ps->fr_ptime[out_FR + 1] += cycles - 1;
- }
- }
- }
-
int
frvbf_model_fr400_u_media_1 (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
--- 621,626 ----
Index: sim/frv/profile-fr500.c
===================================================================
RCS file: /cvs/src/src/sim/frv/profile-fr500.c,v
retrieving revision 1.2
diff -c -p -r1.2 profile-fr500.c
*** sim/frv/profile-fr500.c 12 Sep 2003 22:05:21 -0000 1.2
--- sim/frv/profile-fr500.c 24 Sep 2003 18:52:22 -0000
*************** frvbf_model_fr500_u_clrfr (SIM_CPU *cpu,
*** 580,585 ****
--- 580,620 ----
}
int
+ frvbf_model_fr500_u_commit (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRk, INT in_FRk)
+ {
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* If GR is specified, then FR is not and vice-versa. If neither is
+ then it's a commitga or commitfa. Check the insn attribute to
+ figure out which. */
+ if (in_GRk != -1)
+ vliw_wait_for_SPR (cpu, GNER_FOR_GR (in_GRk));
+ else if (in_FRk != -1)
+ vliw_wait_for_SPR (cpu, FNER_FOR_FR (in_FRk));
+ else if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_FR_ACCESS))
+ {
+ vliw_wait_for_SPR (cpu, H_SPR_FNER0);
+ vliw_wait_for_SPR (cpu, H_SPR_FNER1);
+ }
+ else
+ {
+ vliw_wait_for_SPR (cpu, H_SPR_GNER0);
+ vliw_wait_for_SPR (cpu, H_SPR_GNER1);
+ }
+ handle_resource_wait (cpu);
+ trace_vliw_wait_cycles (cpu);
+ return 0;
+ }
+
+ cycles = idesc->timing->units[unit_num].done;
+ return cycles;
+ }
+
+ int
frvbf_model_fr500_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT out_GRkhi, INT out_GRklo)
*************** frvbf_model_fr500_u_gr_load (SIM_CPU *cp
*** 656,664 ****
update_GR_latency_for_load (cpu, out_GRk, cycles);
update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles);
! set_use_is_gr_complex (cpu, out_GRk);
! set_use_is_gr_complex (cpu, out_GRdoublek);
! set_use_is_gr_complex (cpu, out_GRdoublek + 1);
return cycles;
}
--- 691,710 ----
update_GR_latency_for_load (cpu, out_GRk, cycles);
update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles);
! if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
! {
! /* GNER has a latency of 2 cycles. */
! update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 2);
! update_SPR_latency (cpu, GNER_FOR_GR (out_GRdoublek), cycles + 2);
! }
!
! if (out_GRk >= 0)
! set_use_is_gr_complex (cpu, out_GRk);
! if (out_GRdoublek != -1)
! {
! set_use_is_gr_complex (cpu, out_GRdoublek);
! set_use_is_gr_complex (cpu, out_GRdoublek + 1);
! }
return cycles;
}
*************** frvbf_model_fr500_u_fr_load (SIM_CPU *cp
*** 786,791 ****
--- 832,842 ----
vliw_wait_for_GR (cpu, in_GRj);
vliw_wait_for_FR (cpu, out_FRk);
vliw_wait_for_FRdouble (cpu, out_FRdoublek);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ vliw_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
+ vliw_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek));
+ }
handle_resource_wait (cpu);
load_wait_for_GR (cpu, in_GRi);
load_wait_for_GR (cpu, in_GRj);
*************** frvbf_model_fr500_u_fr_load (SIM_CPU *cp
*** 802,807 ****
--- 853,865 ----
update_FR_latency_for_load (cpu, out_FRk, cycles);
update_FRdouble_latency_for_load (cpu, out_FRdoublek, cycles);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ /* FNER has a latency of 3 cycles. */
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), cycles + 3);
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), cycles + 3);
+ }
+
fr500_reset_fr_flags (cpu, out_FRk);
return cycles;
*************** frvbf_model_fr500_u_gr2fr (SIM_CPU *cpu,
*** 1061,1067 ****
if (use_is_media (cpu, out_FRk))
decrease_FR_busy (cpu, out_FRk, 1);
else
! adjust_float_register_busy (cpu, -1, out_FRk, -1, 1);
}
vliw_wait_for_GR (cpu, in_GRj);
vliw_wait_for_FR (cpu, out_FRk);
--- 1119,1125 ----
if (use_is_media (cpu, out_FRk))
decrease_FR_busy (cpu, out_FRk, 1);
else
! adjust_float_register_busy (cpu, -1, -1, out_FRk, 1);
}
vliw_wait_for_GR (cpu, in_GRj);
vliw_wait_for_FR (cpu, out_FRk);
*************** frvbf_model_fr500_u_dcul (SIM_CPU *cpu,
*** 1385,1436 ****
return cycles;
}
- /* Top up the post-processing time of the given FR by the given number of
- cycles. */
- static void
- update_FR_ptime (SIM_CPU *cpu, INT out_FR, int cycles)
- {
- if (out_FR >= 0)
- {
- FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
- /* If a load is pending on this register, then add the cycles to
- the post processing time for this register. Otherwise apply it
- directly to the latency of the register. */
- if (! load_pending_for_register (cpu, out_FR, 1, REGTYPE_FR))
- {
- int *fr = ps->fr_latency;
- fr[out_FR] += cycles;
- }
- else
- ps->fr_ptime[out_FR] += cycles;
- }
- }
-
- static void
- update_FRdouble_ptime (SIM_CPU *cpu, INT out_FR, int cycles)
- {
- if (out_FR >= 0)
- {
- FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
- /* If a load is pending on this register, then add the cycles to
- the post processing time for this register. Otherwise apply it
- directly to the latency of the register. */
- if (! load_pending_for_register (cpu, out_FR, 2, REGTYPE_FR))
- {
- int *fr = ps->fr_latency;
- fr[out_FR] += cycles;
- if (out_FR < 63)
- fr[out_FR + 1] += cycles;
- }
- else
- {
- ps->fr_ptime[out_FR] += cycles;
- if (out_FR < 63)
- ps->fr_ptime[out_FR + 1] += cycles;
- }
- }
- }
-
int
frvbf_model_fr500_u_float_arith (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
--- 1443,1448 ----
*************** frvbf_model_fr500_u_float_arith (SIM_CPU
*** 1460,1465 ****
--- 1472,1482 ----
post_wait_for_FRdouble (cpu, in_FRdoublei);
post_wait_for_FRdouble (cpu, in_FRdoublej);
post_wait_for_FRdouble (cpu, out_FRdoublek);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
+ post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek));
+ }
restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
1);
*************** frvbf_model_fr500_u_float_arith (SIM_CPU
*** 1468,1477 ****
--- 1485,1506 ----
update_FR_latency (cpu, out_FRk, ps->post_wait);
update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait);
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait);
+ }
+
/* Once initiated, post-processing will take 3 cycles. */
update_FR_ptime (cpu, out_FRk, 3);
update_FRdouble_ptime (cpu, out_FRdoublek, 3);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3);
+ update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3);
+ }
+
/* Mark this use of the register as a floating point op. */
if (out_FRk >= 0)
set_use_is_fpop (cpu, out_FRk);
*************** frvbf_model_fr500_u_float_dual_arith (SI
*** 1536,1541 ****
--- 1565,1577 ----
post_wait_for_FRdouble (cpu, dual_FRdoublei);
post_wait_for_FRdouble (cpu, dual_FRdoublej);
post_wait_for_FRdouble (cpu, dual_FRdoublek);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
+ post_wait_for_SPR (cpu, FNER_FOR_FR (dual_FRk));
+ post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek));
+ post_wait_for_SPR (cpu, FNER_FOR_FR (dual_FRdoublek));
+ }
restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
restore_float_register_busy (cpu, dual_FRi, dual_FRj, dual_FRk, 1);
restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
*************** frvbf_model_fr500_u_float_dual_arith (SI
*** 1549,1560 ****
--- 1585,1612 ----
update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
update_FRdouble_latency (cpu, dual_FRdoublek, ps->post_wait);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait);
+ update_SPR_latency (cpu, FNER_FOR_FR (dual_FRk), ps->post_wait);
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait);
+ update_SPR_latency (cpu, FNER_FOR_FR (dual_FRdoublek), ps->post_wait);
+ }
+
/* Once initiated, post-processing will take 3 cycles. */
update_FR_ptime (cpu, out_FRk, 3);
update_FR_ptime (cpu, dual_FRk, 3);
update_FRdouble_ptime (cpu, out_FRdoublek, 3);
update_FRdouble_ptime (cpu, dual_FRdoublek, 3);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3);
+ update_SPR_ptime (cpu, FNER_FOR_FR (dual_FRk), 3);
+ update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3);
+ update_SPR_ptime (cpu, FNER_FOR_FR (dual_FRdoublek), 3);
+ }
+
/* Mark this use of the register as a floating point op. */
if (out_FRk >= 0)
set_use_is_fpop (cpu, out_FRk);
*************** frvbf_model_fr500_u_float_div (SIM_CPU *
*** 1599,1604 ****
--- 1651,1658 ----
post_wait_for_FR (cpu, in_FRi);
post_wait_for_FR (cpu, in_FRj);
post_wait_for_FR (cpu, out_FRk);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
vliw = CPU_VLIW (cpu);
slot = vliw->next_slot - 1;
slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
*************** frvbf_model_fr500_u_float_div (SIM_CPU *
*** 1610,1615 ****
--- 1664,1676 ----
update_FR_latency (cpu, out_FRk, ps->post_wait);
update_FR_ptime (cpu, out_FRk, 10);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ /* FNER has a latency of 10 cycles. */
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait);
+ update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 10);
+ }
+
/* The latency of the fdiv unit will be at least the latency of the other
inputs. Once initiated, post-processing will take 9 cycles. */
update_fdiv_resource_latency (cpu, slot, ps->post_wait + 9);
*************** frvbf_model_fr500_u_float_sqrt (SIM_CPU
*** 1646,1651 ****
--- 1707,1714 ----
post_wait_for_FR (cpu, out_FRk);
post_wait_for_FRdouble (cpu, in_FRdoublej);
post_wait_for_FRdouble (cpu, out_FRdoublek);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
vliw = CPU_VLIW (cpu);
slot = vliw->next_slot - 1;
slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
*************** frvbf_model_fr500_u_float_sqrt (SIM_CPU
*** 1656,1666 ****
--- 1719,1734 ----
/* The latency of FRk will be at least the latency of the other inputs. */
update_FR_latency (cpu, out_FRk, ps->post_wait);
update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait);
/* Once initiated, post-processing will take 15 cycles. */
update_FR_ptime (cpu, out_FRk, 15);
update_FRdouble_ptime (cpu, out_FRdoublek, 15);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 15);
+
/* The latency of the sqrt unit will be the latency of the other
inputs plus 14 cycles. */
update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14);
*************** frvbf_model_fr500_u_float_convert (SIM_C
*** 1844,1849 ****
--- 1912,1923 ----
post_wait_for_FR (cpu, out_FRk);
post_wait_for_FR (cpu, out_FRintk);
post_wait_for_FRdouble (cpu, out_FRdoublek);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRk));
+ post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRintk));
+ post_wait_for_SPR (cpu, FNER_FOR_FR (out_FRdoublek));
+ }
restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
restore_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
restore_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
*************** frvbf_model_fr500_u_float_convert (SIM_C
*** 1853,1863 ****
--- 1927,1951 ----
update_FR_latency (cpu, out_FRintk, ps->post_wait);
update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRk), ps->post_wait);
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRintk), ps->post_wait);
+ update_SPR_latency (cpu, FNER_FOR_FR (out_FRdoublek), ps->post_wait);
+ }
+
/* Once initiated, post-processing will take 3 cycles. */
update_FR_ptime (cpu, out_FRk, 3);
update_FR_ptime (cpu, out_FRintk, 3);
update_FRdouble_ptime (cpu, out_FRdoublek, 3);
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ update_SPR_ptime (cpu, FNER_FOR_FR (out_FRk), 3);
+ update_SPR_ptime (cpu, FNER_FOR_FR (out_FRintk), 3);
+ update_SPR_ptime (cpu, FNER_FOR_FR (out_FRdoublek), 3);
+ }
+
/* Mark this use of the register as a floating point op. */
if (out_FRk >= 0)
set_use_is_fpop (cpu, out_FRk);
*************** frvbf_model_fr500_u_media_dual_expand (S
*** 2632,2638 ****
if (dual_FRk >= 0)
fr[dual_FRk] += busy_adjustment[2];
! /* The latency of tht output register will be at least the latency of the
other inputs. Once initiated, post-processing will take 3 cycles. */
update_FR_latency (cpu, out_FRk, ps->post_wait);
update_FR_ptime (cpu, out_FRk, 3);
--- 2720,2726 ----
if (dual_FRk >= 0)
fr[dual_FRk] += busy_adjustment[2];
! /* The latency of the output register will be at least the latency of the
other inputs. Once initiated, post-processing will take 3 cycles. */
update_FR_latency (cpu, out_FRk, ps->post_wait);
update_FR_ptime (cpu, out_FRk, 3);
Index: sim/frv/profile.c
===================================================================
RCS file: /cvs/src/src/sim/frv/profile.c,v
retrieving revision 1.3
diff -c -p -r1.3 profile.c
*** sim/frv/profile.c 12 Sep 2003 22:05:22 -0000 1.3
--- sim/frv/profile.c 24 Sep 2003 18:52:22 -0000
*************** update_FRdouble_latency_for_load (SIM_CP
*** 1155,1160 ****
--- 1155,1206 ----
/* Top up the post-processing time of the given FR by the given number of
cycles. */
void
+ update_FR_ptime (SIM_CPU *cpu, INT out_FR, int cycles)
+ {
+ if (out_FR >= 0)
+ {
+ FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+ /* If a load is pending on this register, then add the cycles to
+ the post processing time for this register. Otherwise apply it
+ directly to the latency of the register. */
+ if (! load_pending_for_register (cpu, out_FR, 1, REGTYPE_FR))
+ {
+ int *fr = ps->fr_latency;
+ fr[out_FR] += cycles;
+ }
+ else
+ ps->fr_ptime[out_FR] += cycles;
+ }
+ }
+
+ void
+ update_FRdouble_ptime (SIM_CPU *cpu, INT out_FR, int cycles)
+ {
+ if (out_FR >= 0)
+ {
+ FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+ /* If a load is pending on this register, then add the cycles to
+ the post processing time for this register. Otherwise apply it
+ directly to the latency of the register. */
+ if (! load_pending_for_register (cpu, out_FR, 2, REGTYPE_FR))
+ {
+ int *fr = ps->fr_latency;
+ fr[out_FR] += cycles;
+ if (out_FR < 63)
+ fr[out_FR + 1] += cycles;
+ }
+ else
+ {
+ ps->fr_ptime[out_FR] += cycles;
+ if (out_FR < 63)
+ ps->fr_ptime[out_FR + 1] += cycles;
+ }
+ }
+ }
+
+ /* Top up the post-processing time of the given ACC by the given number of
+ cycles. */
+ void
update_ACC_ptime (SIM_CPU *cpu, INT out_ACC, int cycles)
{
if (out_ACC >= 0)
*************** update_ACC_ptime (SIM_CPU *cpu, INT out_
*** 1167,1172 ****
--- 1213,1233 ----
}
}
+ /* Top up the post-processing time of the given SPR by the given number of
+ cycles. */
+ void
+ update_SPR_ptime (SIM_CPU *cpu, INT out_SPR, int cycles)
+ {
+ if (out_SPR >= 0)
+ {
+ FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+ /* No load can be pending on this register. Apply the cycles
+ directly to the latency of the register. */
+ int *spr = ps->spr_latency;
+ spr[out_SPR] += cycles;
+ }
+ }
+
void
decrease_ACC_busy (SIM_CPU *cpu, INT out_ACC, int cycles)
{
*************** decrease_ACC_busy (SIM_CPU *cpu, INT out
*** 1181,1186 ****
--- 1242,1267 ----
}
}
+ /* start-sanitize-frv */
+ void
+ increase_ACC_busy (SIM_CPU *cpu, INT out_ACC, int cycles)
+ {
+ if (out_ACC >= 0)
+ {
+ FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+ int *acc = ps->acc_busy;
+ acc[out_ACC] += cycles;
+ }
+ }
+
+ void
+ enforce_full_acc_latency (SIM_CPU *cpu, INT in_ACC)
+ {
+ FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+ ps->acc_busy_adjust [in_ACC] = -1;
+ }
+
+ /* end-sanitize-frv */
void
decrease_FR_busy (SIM_CPU *cpu, INT out_FR, int cycles)
{
*************** vliw_wait_for_fdiv_resource (SIM_CPU *cp
*** 1465,1471 ****
{
if (TRACE_INSN_P (cpu))
{
! sprintf (hazard_name, "Resource hazard for integer division in slot I%d:", in_resource);
}
ps->vliw_wait = r[in_resource];
}
--- 1546,1552 ----
{
if (TRACE_INSN_P (cpu))
{
! sprintf (hazard_name, "Resource hazard for floating point division in slot F%d:", in_resource);
}
ps->vliw_wait = r[in_resource];
}
*************** vliw_wait_for_fsqrt_resource (SIM_CPU *c
*** 1485,1491 ****
{
if (TRACE_INSN_P (cpu))
{
! sprintf (hazard_name, "Resource hazard for integer division in slot I%d:", in_resource);
}
ps->vliw_wait = r[in_resource];
}
--- 1566,1572 ----
{
if (TRACE_INSN_P (cpu))
{
! sprintf (hazard_name, "Resource hazard for square root in slot F%d:", in_resource);
}
ps->vliw_wait = r[in_resource];
}
*************** post_wait_for_CCR (SIM_CPU *cpu, INT in_
*** 1690,1695 ****
--- 1771,1790 ----
else
sprintf (hazard_name, "Data hazard for fcc%d:", in_CCR);
}
+ }
+ }
+
+ int
+ post_wait_for_SPR (SIM_CPU *cpu, INT in_SPR)
+ {
+ FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+ int *spr = ps->spr_busy;
+
+ if (in_SPR >= 0 && spr[in_SPR] > ps->post_wait)
+ {
+ ps->post_wait = spr[in_SPR];
+ if (TRACE_INSN_P (cpu))
+ sprintf (hazard_name, "Data hazard for spr[%d]:", in_SPR);
}
}
Index: sim/frv/profile.h
===================================================================
RCS file: /cvs/src/src/sim/frv/profile.h,v
retrieving revision 1.2
diff -c -p -r1.2 profile.h
*** sim/frv/profile.h 12 Sep 2003 22:05:22 -0000 1.2
--- sim/frv/profile.h 24 Sep 2003 18:52:23 -0000
*************** void update_FR_latency (SIM_CPU *, INT,
*** 111,116 ****
--- 111,118 ----
void update_FRdouble_latency (SIM_CPU *, INT, int);
void update_FR_latency_for_load (SIM_CPU *, INT, int);
void update_FRdouble_latency_for_load (SIM_CPU *, INT, int);
+ void update_FR_ptime (SIM_CPU *, INT, int);
+ void update_FRdouble_ptime (SIM_CPU *, INT, int);
void decrease_ACC_busy (SIM_CPU *, INT, int);
void decrease_FR_busy (SIM_CPU *, INT, int);
void decrease_GR_busy (SIM_CPU *, INT, int);
*************** void update_fdiv_resource_latency (SIM_C
*** 123,128 ****
--- 125,131 ----
void update_fsqrt_resource_latency (SIM_CPU *, INT, int);
void update_branch_penalty (SIM_CPU *, int);
void update_ACC_ptime (SIM_CPU *, INT, int);
+ void update_SPR_ptime (SIM_CPU *, INT, int);
void vliw_wait_for_GR (SIM_CPU *, INT);
void vliw_wait_for_GRdouble (SIM_CPU *, INT);
void vliw_wait_for_FR (SIM_CPU *, INT);
*************** int post_wait_for_FR (SIM_CPU *, INT);
*** 142,147 ****
--- 145,151 ----
int post_wait_for_FRdouble (SIM_CPU *, INT);
int post_wait_for_ACC (SIM_CPU *, INT);
int post_wait_for_CCR (SIM_CPU *, INT);
+ int post_wait_for_SPR (SIM_CPU *, INT);
int post_wait_for_fdiv (SIM_CPU *, INT);
int post_wait_for_fsqrt (SIM_CPU *, INT);
Index: sim/frv/sem.c
===================================================================
RCS file: /cvs/src/src/sim/frv/sem.c,v
retrieving revision 1.3
diff -c -p -r1.3 sem.c
*** sim/frv/sem.c 12 Sep 2003 22:05:22 -0000 1.3
--- sim/frv/sem.c 24 Sep 2003 18:52:24 -0000
*************** frvbf_load_quad_FRint (current_cpu, pc,
*** 5317,5351 ****
#undef FLD
}
- /* nldqi: nldqi$pack @($GRi,$d12),$GRk */
-
- static SEM_PC
- SEM_FN_NAME (frvbf,nldqi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
- {
- #define FLD(f) abuf->fields.sfmt_stdi.f
- ARGBUF *abuf = SEM_ARGBUF (sem_arg);
- int UNUSED written = 0;
- IADDR UNUSED pc = abuf->addr;
- SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
- {
- SI tmp_address;
- {
- BI tmp_do_op;
- tmp_do_op = frvbf_check_non_excepting_load (current_cpu, FLD (f_GRi), -1, FLD (f_GRk), FLD (f_d12), 6, 0);
- if (tmp_do_op) {
- {
- tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), FLD (f_d12));
- frvbf_load_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk));
- }
- }
- }
- }
-
- return vpc;
- #undef FLD
- }
-
/* nldqfi: nldqfi$pack @($GRi,$d12),$FRintk */
static SEM_PC
--- 5317,5322 ----
*************** SEM_FN_NAME (frvbf,mwtaccg) (SIM_CPU *cu
*** 27777,27787 ****
--- 27748,27761 ----
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+ {
+ frv_ref_SI (GET_H_ACCG (FLD (f_ACCGk)));
{
USI opval = GET_H_FR_INT (FLD (f_FRi));
sim_queue_fn_si_write (current_cpu, frvbf_h_accg_set, FLD (f_ACCGk), opval);
TRACE_RESULT (current_cpu, abuf, "accg", 'x', opval);
}
+ }
return vpc;
#undef FLD
*************** static const struct sem_fn_desc sem_fns[
*** 28009,28015 ****
{ FRVBF_INSN_NLDDFI, SEM_FN_NAME (frvbf,nlddfi) },
{ FRVBF_INSN_LDQI, SEM_FN_NAME (frvbf,ldqi) },
{ FRVBF_INSN_LDQFI, SEM_FN_NAME (frvbf,ldqfi) },
- { FRVBF_INSN_NLDQI, SEM_FN_NAME (frvbf,nldqi) },
{ FRVBF_INSN_NLDQFI, SEM_FN_NAME (frvbf,nldqfi) },
{ FRVBF_INSN_STB, SEM_FN_NAME (frvbf,stb) },
{ FRVBF_INSN_STH, SEM_FN_NAME (frvbf,sth) },
--- 27983,27988 ----