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[patch] Add fr550 support to the FRV simulator
- From: Dave Brolley <brolley at redhat dot com>
- To: gdb-patches at sources dot redhat dot com
- Date: Mon, 06 Oct 2003 17:17:12 -0400
- Subject: [patch] Add fr550 support to the FRV simulator
- Organization: Red Hat Canada, Ltd
The attached patch adds fr550 support to the FRV simulator. I will
commit it once the necessary binutils patch has been approved and committed.
Dave
2003-10-06 Dave Brolley <brolley@redhat.com>
* profile-fr550.[ch]: New files.
* configure.in: Move frv handling to alphabetically correct placement.
* Makefile.in: Add fr550 support.
* frv-sim.h,frv.c,interrups.c,memory.c,mloop.in,pipeline.c,
profile.[ch],registers.c,traps.c: Add fr550 support.
? sim/frv/profile-fr550.c
? sim/frv/profile-fr550.h
Index: sim/configure.in
===================================================================
RCS file: /cvs/src/src/sim/configure.in,v
retrieving revision 1.13
diff -c -p -r1.13 configure.in
*** sim/configure.in 29 Aug 2003 16:45:22 -0000 1.13
--- sim/configure.in 6 Oct 2003 20:12:44 -0000
*************** case "${target}" in
*** 65,75 ****
# OBSOLETE extra_subdirs="${extra_subdirs} igen"
# OBSOLETE ;;
# OBSOLETE fr30-*-*) sim_target=fr30 ;;
! h8300*-*-*)
! sim_target=h8300
extra_subdirs="${extra_subdirs} testsuite"
;;
! frv-*-*) sim_target=frv
extra_subdirs="${extra_subdirs} testsuite"
;;
h8500-*-*) sim_target=h8500 ;;
--- 65,75 ----
# OBSOLETE extra_subdirs="${extra_subdirs} igen"
# OBSOLETE ;;
# OBSOLETE fr30-*-*) sim_target=fr30 ;;
! frv-*-*) sim_target=frv
extra_subdirs="${extra_subdirs} testsuite"
;;
! h8300*-*-*)
! sim_target=h8300
extra_subdirs="${extra_subdirs} testsuite"
;;
h8500-*-*) sim_target=h8500 ;;
Index: sim/frv/Makefile.in
===================================================================
RCS file: /cvs/src/src/sim/frv/Makefile.in,v
retrieving revision 1.2
diff -c -p -r1.2 Makefile.in
*** sim/frv/Makefile.in 8 Sep 2003 17:25:35 -0000 1.2
--- sim/frv/Makefile.in 6 Oct 2003 20:12:44 -0000
*************** SIM_OBJS = \
*** 35,41 ****
sim-if.o arch.o \
$(FRV_OBJS) \
traps.o interrupts.o memory.o cache.o pipeline.o \
! profile.o profile-fr400.o profile-fr500.o options.o \
devices.o reset.o registers.o \
$(CONFIG_DEVICES)
--- 35,41 ----
sim-if.o arch.o \
$(FRV_OBJS) \
traps.o interrupts.o memory.o cache.o pipeline.o \
! profile.o profile-fr400.o profile-fr500.o profile-fr550.o options.o \
devices.o reset.o registers.o \
$(CONFIG_DEVICES)
*************** cache.o: cache.c $(FRVBF_INCLUDE_DEPS)
*** 78,86 ****
options.o: options.c $(FRVBF_INCLUDE_DEPS)
reset.o: reset.c $(FRVBF_INCLUDE_DEPS)
registers.o: registers.c $(FRVBF_INCLUDE_DEPS)
! profile.o: profile.c profile-fr400.h profile-fr500.h $(FRVBF_INCLUDE_DEPS)
profile-fr400.o: profile-fr400.c profile-fr400.h $(FRVBF_INCLUDE_DEPS)
profile-fr500.o: profile-fr500.c profile-fr500.h $(FRVBF_INCLUDE_DEPS)
sim-if.o: sim-if.c $(FRVBF_INCLUDE_DEPS) $(srcdir)/../common/sim-core.h eng.h
--- 78,87 ----
options.o: options.c $(FRVBF_INCLUDE_DEPS)
reset.o: reset.c $(FRVBF_INCLUDE_DEPS)
registers.o: registers.c $(FRVBF_INCLUDE_DEPS)
! profile.o: profile.c profile-fr400.h profile-fr500.h profile-fr550.h $(FRVBF_INCLUDE_DEPS)
profile-fr400.o: profile-fr400.c profile-fr400.h $(FRVBF_INCLUDE_DEPS)
profile-fr500.o: profile-fr500.c profile-fr500.h $(FRVBF_INCLUDE_DEPS)
+ profile-fr550.o: profile-fr550.c profile-fr550.h $(FRVBF_INCLUDE_DEPS)
sim-if.o: sim-if.c $(FRVBF_INCLUDE_DEPS) $(srcdir)/../common/sim-core.h eng.h
*************** arch.h arch.c cpuall.h: $(CGEN_MAINT) st
*** 120,126 ****
stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srcdir)/../../cpu/frv.cpu
$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
! cpu=frvbf mach=frv,fr500,fr400,tomcat,simple SUFFIX= \
archfile=$(srcdir)/../../cpu/frv.cpu \
FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" \
EXTRAFILES="$(CGEN_CPU_SEM)"
--- 121,127 ----
stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srcdir)/../../cpu/frv.cpu
$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
! cpu=frvbf mach=frv,fr550,fr500,fr400,tomcat,simple SUFFIX= \
archfile=$(srcdir)/../../cpu/frv.cpu \
FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" \
EXTRAFILES="$(CGEN_CPU_SEM)"
Index: sim/frv/frv-sim.h
===================================================================
RCS file: /cvs/src/src/sim/frv/frv-sim.h,v
retrieving revision 1.2
diff -c -p -r1.2 frv-sim.h
*** sim/frv/frv-sim.h 12 Sep 2003 22:05:21 -0000 1.2
--- sim/frv/frv-sim.h 6 Oct 2003 20:12:44 -0000
***************
*** 1,6 ****
/* collection of junk waiting time to sort out
Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
! Contributed by Red Hat.
This file is part of the GNU Simulators.
--- 1,6 ----
/* collection of junk waiting time to sort out
Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
! Contributed by Red Hat
This file is part of the GNU Simulators.
*************** extern void frvbf_switch_supervisor_user
*** 104,111 ****
--- 104,114 ----
extern QI frvbf_set_icc_for_shift_left (SIM_CPU *, SI, SI, QI);
extern QI frvbf_set_icc_for_shift_right (SIM_CPU *, SI, SI, QI);
+ /* Insn semantics. */
extern void frvbf_signed_integer_divide (SIM_CPU *, SI, SI, int, int);
extern void frvbf_unsigned_integer_divide (SIM_CPU *, USI, USI, int, int);
+ extern SI frvbf_shift_left_arith_saturate (SIM_CPU *, SI, SI);
+ extern SI frvbf_iacc_cut (SIM_CPU *, DI, SI);
extern void frvbf_clear_accumulators (SIM_CPU *, SI, int);
*************** struct _device { int foo; };
*** 149,154 ****
--- 152,158 ----
/* maintain the address of the start of the previous VLIW insn sequence. */
extern IADDR previous_vliw_pc;
+ extern CGEN_ATTR_VALUE_TYPE frv_current_fm_slot;
/* Hardware status. */
#define GET_HSR0() GET_H_SPR (H_SPR_HSR0)
*************** extern IADDR previous_vliw_pc;
*** 174,179 ****
--- 178,186 ----
#define GET_IHSR8() GET_H_SPR (H_SPR_IHSR8)
#define GET_IHSR8_NBC(ihsr8) ((ihsr8) & 1)
+ #define GET_IHSR8_ICDM(ihsr8) (((ihsr8) >> 1) & 1)
+ #define GET_IHSR8_ICWE(ihsr8) (((ihsr8) >> 8) & 7)
+ #define GET_IHSR8_DCWE(ihsr8) (((ihsr8) >> 12) & 7)
void frvbf_insn_cache_preload (SIM_CPU *, SI, USI, int);
void frvbf_data_cache_preload (SIM_CPU *, SI, USI, int);
*************** enum frv_msr_mtt
*** 645,650 ****
--- 652,660 ----
#define GET_MSR_EMCI(msr) ( \
((msr) >> 24) & 0x1 \
)
+ #define GET_MSR_MPEM(msr) ( \
+ ((msr) >> 27) & 0x1 \
+ )
#define GET_MSR_SRDAV(msr) ( \
((msr) >> 28) & 0x1 \
)
*************** frv_queue_external_interrupt (SIM_CPU *,
*** 675,680 ****
--- 685,699 ----
struct frv_interrupt_queue_element *
frv_queue_illegal_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
+
+ struct frv_interrupt_queue_element *
+ frv_queue_privileged_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
+
+ struct frv_interrupt_queue_element *
+ frv_queue_float_disabled_interrupt (SIM_CPU *);
+
+ struct frv_interrupt_queue_element *
+ frv_queue_media_disabled_interrupt (SIM_CPU *);
struct frv_interrupt_queue_element *
frv_queue_non_implemented_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
Index: sim/frv/frv.c
===================================================================
RCS file: /cvs/src/src/sim/frv/frv.c,v
retrieving revision 1.2
diff -c -p -r1.2 frv.c
*** sim/frv/frv.c 9 Sep 2003 22:28:33 -0000 1.2
--- sim/frv/frv.c 6 Oct 2003 20:12:44 -0000
*************** check_register_alignment (SIM_CPU *curre
*** 113,118 ****
--- 113,119 ----
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
+ case bfd_mach_fr550:
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
break;
case bfd_mach_frvtomcat:
*************** check_fr_register_alignment (SIM_CPU *cu
*** 140,145 ****
--- 141,147 ----
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
+ case bfd_mach_fr550:
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
break;
case bfd_mach_frvtomcat:
*************** frvbf_h_spr_set_handler (SIM_CPU *curren
*** 431,436 ****
--- 433,441 ----
case H_SPR_SR3:
spr_sr_set_handler (current_cpu, spr, newval);
break;
+ case H_SPR_IHSR8:
+ frv_cache_reconfigure (current_cpu, CPU_INSN_CACHE (current_cpu));
+ break;
default:
CPU (h_spr[spr]) = newval;
break;
*************** frvbf_clear_accumulators (SIM_CPU *curre
*** 926,934 ****
--- 931,943 ----
SIM_DESC sd = CPU_STATE (current_cpu);
int acc_num =
(STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500) ? 8 :
+ (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) ? 8 :
(STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) ? 4 :
63;
+ FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
+ ps->mclracc_acc = acc_ix;
+ ps->mclracc_A = A;
if (A == 0 || acc_ix != 0) /* Clear 1 accumuator? */
{
/* This instruction is a nop if the referenced accumulator is not
*************** frvbf_media_cut_ss (SIM_CPU *current_cpu
*** 1027,1032 ****
--- 1036,1100 ----
return frvbf_media_cut (current_cpu, acc, cut_point);
}
+ /* Compute the result of int accumulator cut (SCUTSS). */
+ SI
+ frvbf_iacc_cut (SIM_CPU *current_cpu, DI acc, SI cut_point)
+ {
+ /* The cut point is the lower 6 bits (signed) of what we are passed. */
+ cut_point = cut_point << 25 >> 25;
+
+ if (cut_point <= -32)
+ cut_point = -31; /* Special case for full shiftout. */
+
+ /* Negative cuts (cannot saturate). */
+ if (cut_point < 0)
+ return acc >> (32 + -cut_point);
+
+ /* Positive cuts will saturate if significant bits are shifted out. */
+ if (acc != ((acc << cut_point) >> cut_point))
+ if (acc >= 0)
+ return 0x7fffffff;
+ else
+ return 0x80000000;
+
+ /* No saturate, just cut. */
+ return ((acc << cut_point) >> 32);
+ }
+
+ /* Compute the result of shift-left-arithmetic-with-saturation (SLASS). */
+ SI
+ frvbf_shift_left_arith_saturate (SIM_CPU *current_cpu, SI arg1, SI arg2)
+ {
+ int neg_arg1;
+
+ /* FIXME: what to do with negative shift amt? */
+ if (arg2 <= 0)
+ return arg1;
+
+ if (arg1 == 0)
+ return 0;
+
+ /* Signed shift by 31 or greater saturates by definition. */
+ if (arg2 >= 31)
+ if (arg1 > 0)
+ return (SI) 0x7fffffff;
+ else
+ return (SI) 0x80000000;
+
+ /* OK, arg2 is between 1 and 31. */
+ neg_arg1 = (arg1 < 0);
+ do {
+ arg1 <<= 1;
+ /* Check for sign bit change (saturation). */
+ if (neg_arg1 && (arg1 >= 0))
+ return (SI) 0x80000000;
+ else if (!neg_arg1 && (arg1 < 0))
+ return (SI) 0x7fffffff;
+ } while (--arg2 > 0);
+
+ return arg1;
+ }
+
/* Simulate the media custom insns. */
void
frvbf_media_cop (SIM_CPU *current_cpu, int cop_num)
*************** do_media_average (SIM_CPU *current_cpu,
*** 1051,1062 ****
HI result = sum >> 1;
int rounding_value;
! /* On fr400, check the rounding mode. On other machines rounding is always
toward negative infinity and the result is already correctly rounded. */
switch (STATE_ARCHITECTURE (sd)->mach)
{
/* Need to check rounding mode. */
case bfd_mach_fr400:
/* Check whether rounding will be required. Rounding will be required
if the sum is an odd number. */
rounding_value = sum & 1;
--- 1119,1131 ----
HI result = sum >> 1;
int rounding_value;
! /* On fr400 and fr550, check the rounding mode. On other machines rounding is always
toward negative infinity and the result is already correctly rounded. */
switch (STATE_ARCHITECTURE (sd)->mach)
{
/* Need to check rounding mode. */
case bfd_mach_fr400:
+ case bfd_mach_fr550:
/* Check whether rounding will be required. Rounding will be required
if the sum is an odd number. */
rounding_value = sum & 1;
Index: sim/frv/interrupts.c
===================================================================
RCS file: /cvs/src/src/sim/frv/interrupts.c,v
retrieving revision 1.1
diff -c -p -r1.1 interrupts.c
*** sim/frv/interrupts.c 29 Aug 2003 16:35:46 -0000 1.1
--- sim/frv/interrupts.c 6 Oct 2003 20:12:45 -0000
*************** frv_queue_illegal_instruction_interrupt
*** 235,244 ****
SIM_CPU *current_cpu, const CGEN_INSN *insn
)
{
- /* The fr400 does not have the fp_exception. */
SIM_DESC sd = CPU_STATE (current_cpu);
! if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr400)
{
if (frv_is_float_insn (insn) || frv_is_media_insn (insn))
{
struct frv_fp_exception_info fp_info = {
--- 235,248 ----
SIM_CPU *current_cpu, const CGEN_INSN *insn
)
{
SIM_DESC sd = CPU_STATE (current_cpu);
! switch (STATE_ARCHITECTURE (sd)->mach)
{
+ case bfd_mach_fr400:
+ case bfd_mach_fr550:
+ break;
+ default:
+ /* Some machines generate fp_exception for this case. */
if (frv_is_float_insn (insn) || frv_is_media_insn (insn))
{
struct frv_fp_exception_info fp_info = {
*************** frv_queue_illegal_instruction_interrupt
*** 246,266 ****
};
return frv_queue_fp_exception_interrupt (current_cpu, & fp_info);
}
}
return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
}
struct frv_interrupt_queue_element *
frv_queue_non_implemented_instruction_interrupt (
SIM_CPU *current_cpu, const CGEN_INSN *insn
)
{
- /* The fr400 does not have the fp_exception, nor does it generate mp_exception
- for this case. */
SIM_DESC sd = CPU_STATE (current_cpu);
! if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr400)
{
if (frv_is_float_insn (insn))
{
struct frv_fp_exception_info fp_info = {
--- 250,308 ----
};
return frv_queue_fp_exception_interrupt (current_cpu, & fp_info);
}
+ break;
}
return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
}
struct frv_interrupt_queue_element *
+ frv_queue_privileged_instruction_interrupt (SIM_CPU *current_cpu, const CGEN_INSN *insn)
+ {
+ /* The fr550 has no privileged instruction interrupt. It uses
+ illegal_instruction. */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+
+ return frv_queue_program_interrupt (current_cpu, FRV_PRIVILEGED_INSTRUCTION);
+ }
+
+ struct frv_interrupt_queue_element *
+ frv_queue_float_disabled_interrupt (SIM_CPU *current_cpu)
+ {
+ /* The fr550 has no fp_disabled interrupt. It uses illegal_instruction. */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+
+ return frv_queue_program_interrupt (current_cpu, FRV_FP_DISABLED);
+ }
+
+ struct frv_interrupt_queue_element *
+ frv_queue_media_disabled_interrupt (SIM_CPU *current_cpu)
+ {
+ /* The fr550 has no mp_disabled interrupt. It uses illegal_instruction. */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+
+ return frv_queue_program_interrupt (current_cpu, FRV_MP_DISABLED);
+ }
+
+ struct frv_interrupt_queue_element *
frv_queue_non_implemented_instruction_interrupt (
SIM_CPU *current_cpu, const CGEN_INSN *insn
)
{
SIM_DESC sd = CPU_STATE (current_cpu);
! switch (STATE_ARCHITECTURE (sd)->mach)
{
+ case bfd_mach_fr400:
+ case bfd_mach_fr550:
+ break;
+ default:
+ /* Some machines generate fp_exception or mp_exception for this case. */
if (frv_is_float_insn (insn))
{
struct frv_fp_exception_info fp_info = {
*************** frv_queue_non_implemented_instruction_in
*** 268,281 ****
};
return frv_queue_fp_exception_interrupt (current_cpu, & fp_info);
}
-
if (frv_is_media_insn (insn))
{
frv_set_mp_exception_registers (current_cpu, MTT_UNIMPLEMENTED_MPOP,
0);
return NULL; /* no interrupt queued at this time. */
}
!
}
return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
--- 310,322 ----
};
return frv_queue_fp_exception_interrupt (current_cpu, & fp_info);
}
if (frv_is_media_insn (insn))
{
frv_set_mp_exception_registers (current_cpu, MTT_UNIMPLEMENTED_MPOP,
0);
return NULL; /* no interrupt queued at this time. */
}
! break;
}
return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
*************** frv_detect_insn_access_interrupts (SIM_C
*** 364,382 ****
if (frv_is_float_insn (insn)
|| (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR_ACCESS)
&& ! GET_H_PSR_EM ()))
! frv_queue_program_interrupt (current_cpu, FRV_FP_DISABLED);
}
/* Make sure media support is enabled. */
else if (! GET_H_PSR_EM ())
{
/* Generate mp_disabled if it is a media insn. */
if (frv_is_media_insn (insn) || CGEN_INSN_NUM (insn) == FRV_INSN_MTRAP)
! frv_queue_program_interrupt (current_cpu, FRV_MP_DISABLED);
}
/* Check for privileged insns. */
else if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_PRIVILEGED) &&
! GET_H_PSR_S ())
! frv_queue_program_interrupt (current_cpu, FRV_PRIVILEGED_INSTRUCTION);
#if 0 /* disable for now until we find out how FSR0.QNE gets reset. */
else
{
--- 405,423 ----
if (frv_is_float_insn (insn)
|| (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR_ACCESS)
&& ! GET_H_PSR_EM ()))
! frv_queue_float_disabled_interrupt (current_cpu);
}
/* Make sure media support is enabled. */
else if (! GET_H_PSR_EM ())
{
/* Generate mp_disabled if it is a media insn. */
if (frv_is_media_insn (insn) || CGEN_INSN_NUM (insn) == FRV_INSN_MTRAP)
! frv_queue_media_disabled_interrupt (current_cpu);
}
/* Check for privileged insns. */
else if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_PRIVILEGED) &&
! GET_H_PSR_S ())
! frv_queue_privileged_instruction_interrupt (current_cpu, insn);
#if 0 /* disable for now until we find out how FSR0.QNE gets reset. */
else
{
*************** esr_for_data_access_exception (
*** 552,557 ****
--- 593,602 ----
SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item
)
{
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ return 8; /* Use ESR8, EPCR8. */
+
if (item->slot == UNIT_I0)
return 8; /* Use ESR8, EPCR8, EAR8, EDR8. */
*************** clear_exception_status_registers (SIM_CP
*** 593,599 ****
CLEAR_ESR_VALID (esr);
SET_ESR (i, esr);
}
! for (i = 8; i <= 13; ++i)
{
SI esr = GET_ESR (i);
CLEAR_ESR_VALID (esr);
--- 638,644 ----
CLEAR_ESR_VALID (esr);
SET_ESR (i, esr);
}
! for (i = 8; i <= 15; ++i)
{
SI esr = GET_ESR (i);
CLEAR_ESR_VALID (esr);
*************** frv_set_mp_exception_registers (
*** 617,626 ****
{
FRV_VLIW *vliw = CPU_VLIW (current_cpu);
int slot = vliw->next_slot - 1;
/* If this insn is in the M2 slot, then set MSR1.OVF and MSR1.SIE,
otherwise set MSR0.OVF and MSR0.SIE. */
! if ((*vliw->current_vliw)[slot] == UNIT_FM1)
{
SI msr = GET_MSR (1);
OR_MSR_SIE (msr, sie);
--- 662,672 ----
{
FRV_VLIW *vliw = CPU_VLIW (current_cpu);
int slot = vliw->next_slot - 1;
+ SIM_DESC sd = CPU_STATE (current_cpu);
/* If this insn is in the M2 slot, then set MSR1.OVF and MSR1.SIE,
otherwise set MSR0.OVF and MSR0.SIE. */
! if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550 && (*vliw->current_vliw)[slot] == UNIT_FM1)
{
SI msr = GET_MSR (1);
OR_MSR_SIE (msr, sie);
*************** frv_set_mp_exception_registers (
*** 633,640 ****
SET_MSR_OVF (msr0);
}
! /* Regardless of the slot, set MSR0.AOVF. */
! SET_MSR_AOVF (msr0);
}
SET_MSR (0, msr0);
--- 679,692 ----
SET_MSR_OVF (msr0);
}
! /* Generate the interrupt now if MSR0.MPEM is set on fr550 */
! if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550 && GET_MSR_MPEM (msr0))
! frv_queue_program_interrupt (current_cpu, FRV_MP_EXCEPTION);
! else
! {
! /* Regardless of the slot, set MSR0.AOVF. */
! SET_MSR_AOVF (msr0);
! }
}
SET_MSR (0, msr0);
*************** set_fp_exception_registers (
*** 689,694 ****
--- 741,758 ----
SI fsr0;
IADDR pc;
struct frv_fp_exception_info *fp_info;
+ SIM_DESC sd = CPU_STATE (current_cpu);
+
+ /* No FQ registers on fr550 */
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ {
+ /* Update the fsr. */
+ fp_info = & item->u.fp_info;
+ fsr0 = GET_FSR (0);
+ SET_FSR_FTT (fsr0, fp_info->ftt);
+ SET_FSR (0, fsr0);
+ return;
+ }
/* Select an FQ and update it with the exception information. */
fq_index = fq_for_exception (current_cpu, item);
*************** set_exception_status_registers (
*** 755,761 ****
SET_ESR_REC (esr, item->u.rec);
else if (interrupt->kind == FRV_INSTRUCTION_ACCESS_EXCEPTION)
SET_ESR_IAEC (esr, item->u.iaec);
! set_epcr = 1;
}
else
{
--- 819,827 ----
SET_ESR_REC (esr, item->u.rec);
else if (interrupt->kind == FRV_INSTRUCTION_ACCESS_EXCEPTION)
SET_ESR_IAEC (esr, item->u.iaec);
! /* For fr550, don't set epcr for precise interrupts. */
! if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
! set_epcr = 1;
}
else
{
*************** set_exception_status_registers (
*** 765,778 ****
set_isr_exception_fields (current_cpu, item);
/* fall thru to set reg_index. */
case FRV_COMMIT_EXCEPTION:
! if (item->slot == UNIT_I0)
reg_index = 0;
else if (item->slot == UNIT_I1)
reg_index = 1;
set_epcr = 1;
break;
case FRV_DATA_STORE_ERROR:
! reg_index = 14; /* Use ESR15, EPCR15. */
break;
case FRV_DATA_ACCESS_ERROR:
reg_index = 15; /* Use ESR15, EPCR15. */
--- 831,847 ----
set_isr_exception_fields (current_cpu, item);
/* fall thru to set reg_index. */
case FRV_COMMIT_EXCEPTION:
! /* For fr550, always use ESR0. */
! if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
! reg_index = 0;
! else if (item->slot == UNIT_I0)
reg_index = 0;
else if (item->slot == UNIT_I1)
reg_index = 1;
set_epcr = 1;
break;
case FRV_DATA_STORE_ERROR:
! reg_index = 14; /* Use ESR14. */
break;
case FRV_DATA_ACCESS_ERROR:
reg_index = 15; /* Use ESR15, EPCR15. */
*************** set_exception_status_registers (
*** 787,801 ****
/* Get the appropriate ESR, EPCR, EAR and EDR.
EAR will be set. EDR will not be set if this is a store insn. */
set_ear = 1;
! if (item->u.data_written.length != 0)
! set_edr = 1;
reg_index = esr_for_data_access_exception (current_cpu, item);
set_epcr = 1;
break;
case FRV_MP_EXCEPTION:
break; /* MSR0-1, FQ0-9 are already set. */
case FRV_FP_EXCEPTION:
set_fp_exception_registers (current_cpu, item);
break;
default:
{
--- 856,884 ----
/* Get the appropriate ESR, EPCR, EAR and EDR.
EAR will be set. EDR will not be set if this is a store insn. */
set_ear = 1;
! /* For fr550, never use EDRx. */
! if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
! if (item->u.data_written.length != 0)
! set_edr = 1;
reg_index = esr_for_data_access_exception (current_cpu, item);
set_epcr = 1;
break;
case FRV_MP_EXCEPTION:
+ /* For fr550, use EPCR2 and ESR2. */
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ {
+ reg_index = 2;
+ set_epcr = 1;
+ }
break; /* MSR0-1, FQ0-9 are already set. */
case FRV_FP_EXCEPTION:
set_fp_exception_registers (current_cpu, item);
+ /* For fr550, use EPCR2 and ESR2. */
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ {
+ reg_index = 2;
+ set_epcr = 1;
+ }
break;
default:
{
Index: sim/frv/memory.c
===================================================================
RCS file: /cvs/src/src/sim/frv/memory.c,v
retrieving revision 1.1
diff -c -p -r1.1 memory.c
*** sim/frv/memory.c 29 Aug 2003 16:35:46 -0000 1.1
--- sim/frv/memory.c 6 Oct 2003 20:12:45 -0000
***************
*** 1,6 ****
/* frv memory model.
! Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
! Contributed by Red Hat.
This file is part of the GNU simulators.
--- 1,6 ----
/* frv memory model.
! Copyright (C) 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
! Contributed by Red Hat
This file is part of the GNU simulators.
*************** fr500_check_data_read_address (SIM_CPU *
*** 56,61 ****
--- 56,72 ----
}
static SI
+ fr550_check_data_read_address (SIM_CPU *current_cpu, SI address, int align_mask)
+ {
+ if ((USI)address >= 0xfe800000 && (USI)address <= 0xfefeffff
+ || (align_mask > 0x3
+ && ((USI)address >= 0xfeff0000 && (USI)address <= 0xfeffffff)))
+ frv_queue_data_access_error_interrupt (current_cpu, address);
+
+ return address;
+ }
+
+ static SI
check_data_read_address (SIM_CPU *current_cpu, SI address, int align_mask)
{
SIM_DESC sd = CPU_STATE (current_cpu);
*************** check_data_read_address (SIM_CPU *curren
*** 71,76 ****
--- 82,91 ----
address = fr500_check_data_read_address (current_cpu, address,
align_mask);
break;
+ case bfd_mach_fr550:
+ address = fr550_check_data_read_address (current_cpu, address,
+ align_mask);
+ break;
default:
break;
}
*************** fr500_check_readwrite_address (SIM_CPU *
*** 109,114 ****
--- 124,148 ----
}
static SI
+ fr550_check_readwrite_address (SIM_CPU *current_cpu, SI address, int align_mask)
+ {
+ /* No alignment restrictions on fr550 */
+
+ if ((USI)address >= 0xfe000000 && (USI)address <= 0xfe3fffff
+ || (USI)address >= 0xfe408000 && (USI)address <= 0xfe7fffff)
+ frv_queue_data_access_exception_interrupt (current_cpu);
+ else
+ {
+ USI hsr0 = GET_HSR0 ();
+ if (! GET_HSR0_RME (hsr0)
+ && (USI)address >= 0xfe400000 && (USI)address <= 0xfe407fff)
+ frv_queue_data_access_exception_interrupt (current_cpu);
+ }
+
+ return address;
+ }
+
+ static SI
check_readwrite_address (SIM_CPU *current_cpu, SI address, int align_mask)
{
SIM_DESC sd = CPU_STATE (current_cpu);
*************** check_readwrite_address (SIM_CPU *curren
*** 124,129 ****
--- 158,167 ----
address = fr500_check_readwrite_address (current_cpu, address,
align_mask);
break;
+ case bfd_mach_fr550:
+ address = fr550_check_readwrite_address (current_cpu, address,
+ align_mask);
+ break;
default:
break;
}
*************** fr500_check_insn_read_address (SIM_CPU *
*** 175,180 ****
--- 213,239 ----
}
static PCADDR
+ fr550_check_insn_read_address (SIM_CPU *current_cpu, PCADDR address,
+ int align_mask)
+ {
+ address &= ~align_mask;
+
+ if ((USI)address >= 0xfe800000 && (USI)address <= 0xfeffffff)
+ frv_queue_instruction_access_error_interrupt (current_cpu);
+ else if ((USI)address >= 0xfe008000 && (USI)address <= 0xfe7fffff)
+ frv_queue_instruction_access_exception_interrupt (current_cpu);
+ else
+ {
+ USI hsr0 = GET_HSR0 ();
+ if (! GET_HSR0_RME (hsr0)
+ && (USI)address >= 0xfe000000 && (USI)address <= 0xfe007fff)
+ frv_queue_instruction_access_exception_interrupt (current_cpu);
+ }
+
+ return address;
+ }
+
+ static PCADDR
check_insn_read_address (SIM_CPU *current_cpu, PCADDR address, int align_mask)
{
SIM_DESC sd = CPU_STATE (current_cpu);
*************** check_insn_read_address (SIM_CPU *curren
*** 190,195 ****
--- 249,258 ----
address = fr500_check_insn_read_address (current_cpu, address,
align_mask);
break;
+ case bfd_mach_fr550:
+ address = fr550_check_insn_read_address (current_cpu, address,
+ align_mask);
+ break;
default:
break;
}
*************** frvbf_read_mem_UQI (SIM_CPU *current_cpu
*** 262,267 ****
--- 325,340 ----
return GETMEMUQI (current_cpu, pc, address);
}
+ /* Read a HI which spans two cache lines */
+ static HI
+ read_mem_unaligned_HI (SIM_CPU *current_cpu, IADDR pc, SI address)
+ {
+ HI value = frvbf_read_mem_QI (current_cpu, pc, address);
+ value <<= 8;
+ value |= frvbf_read_mem_UQI (current_cpu, pc, address + 1);
+ return T2H_2 (value);
+ }
+
HI
frvbf_read_mem_HI (SIM_CPU *current_cpu, IADDR pc, SI address)
{
*************** frvbf_read_mem_HI (SIM_CPU *current_cpu,
*** 288,293 ****
--- 361,373 ----
if (GET_HSR0_DCE (hsr0))
{
int cycles;
+ /* Handle access which crosses cache line boundary */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ {
+ if (DATA_CROSSES_CACHE_LINE (cache, address, 2))
+ return read_mem_unaligned_HI (current_cpu, pc, address);
+ }
cycles = frv_cache_read (cache, 0, address);
if (cycles != 0)
return CACHE_RETURN_DATA (cache, 0, address, HI, 2);
*************** frvbf_read_mem_UHI (SIM_CPU *current_cpu
*** 322,327 ****
--- 402,414 ----
if (GET_HSR0_DCE (hsr0))
{
int cycles;
+ /* Handle access which crosses cache line boundary */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ {
+ if (DATA_CROSSES_CACHE_LINE (cache, address, 2))
+ return read_mem_unaligned_HI (current_cpu, pc, address);
+ }
cycles = frv_cache_read (cache, 0, address);
if (cycles != 0)
return CACHE_RETURN_DATA (cache, 0, address, UHI, 2);
*************** frvbf_read_mem_UHI (SIM_CPU *current_cpu
*** 330,335 ****
--- 417,460 ----
return GETMEMUHI (current_cpu, pc, address);
}
+ /* Read a SI which spans two cache lines */
+ static SI
+ read_mem_unaligned_SI (SIM_CPU *current_cpu, IADDR pc, SI address)
+ {
+ FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
+ unsigned hi_len = cache->line_size - (address & (cache->line_size - 1));
+ char valarray[4];
+ SI SIvalue;
+ HI HIvalue;
+
+ switch (hi_len)
+ {
+ case 1:
+ valarray[0] = frvbf_read_mem_QI (current_cpu, pc, address);
+ SIvalue = frvbf_read_mem_SI (current_cpu, pc, address + 1);
+ SIvalue = H2T_4 (SIvalue);
+ memcpy (valarray + 1, (char*)&SIvalue, 3);
+ break;
+ case 2:
+ HIvalue = frvbf_read_mem_HI (current_cpu, pc, address);
+ HIvalue = H2T_2 (HIvalue);
+ memcpy (valarray, (char*)&HIvalue, 2);
+ HIvalue = frvbf_read_mem_HI (current_cpu, pc, address + 2);
+ HIvalue = H2T_2 (HIvalue);
+ memcpy (valarray + 2, (char*)&HIvalue, 2);
+ break;
+ case 3:
+ SIvalue = frvbf_read_mem_SI (current_cpu, pc, address - 1);
+ SIvalue = H2T_4 (SIvalue);
+ memcpy (valarray, (char*)&SIvalue, 3);
+ valarray[3] = frvbf_read_mem_QI (current_cpu, pc, address + 3);
+ break;
+ default:
+ abort (); /* can't happen */
+ }
+ return T2H_4 (*(SI*)valarray);
+ }
+
SI
frvbf_read_mem_SI (SIM_CPU *current_cpu, IADDR pc, SI address)
{
*************** frvbf_read_mem_SI (SIM_CPU *current_cpu,
*** 355,360 ****
--- 480,492 ----
if (GET_HSR0_DCE (hsr0))
{
int cycles;
+ /* Handle access which crosses cache line boundary */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ {
+ if (DATA_CROSSES_CACHE_LINE (cache, address, 4))
+ return read_mem_unaligned_SI (current_cpu, pc, address);
+ }
cycles = frv_cache_read (cache, 0, address);
if (cycles != 0)
return CACHE_RETURN_DATA (cache, 0, address, SI, 4);
*************** frvbf_read_mem_WI (SIM_CPU *current_cpu,
*** 369,374 ****
--- 501,579 ----
return frvbf_read_mem_SI (current_cpu, pc, address);
}
+ /* Read a SI which spans two cache lines */
+ static DI
+ read_mem_unaligned_DI (SIM_CPU *current_cpu, IADDR pc, SI address)
+ {
+ FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
+ unsigned hi_len = cache->line_size - (address & (cache->line_size - 1));
+ DI value, value1;
+
+ switch (hi_len)
+ {
+ case 1:
+ value = frvbf_read_mem_QI (current_cpu, pc, address);
+ value <<= 56;
+ value1 = frvbf_read_mem_DI (current_cpu, pc, address + 1);
+ value1 = H2T_8 (value1);
+ value |= value1 & ((DI)0x00ffffff << 32);
+ value |= value1 & 0xffffffffu;
+ break;
+ case 2:
+ value = frvbf_read_mem_HI (current_cpu, pc, address);
+ value = H2T_2 (value);
+ value <<= 48;
+ value1 = frvbf_read_mem_DI (current_cpu, pc, address + 2);
+ value1 = H2T_8 (value1);
+ value |= value1 & ((DI)0x0000ffff << 32);
+ value |= value1 & 0xffffffffu;
+ break;
+ case 3:
+ value = frvbf_read_mem_SI (current_cpu, pc, address - 1);
+ value = H2T_4 (value);
+ value <<= 40;
+ value1 = frvbf_read_mem_DI (current_cpu, pc, address + 3);
+ value1 = H2T_8 (value1);
+ value |= value1 & ((DI)0x000000ff << 32);
+ value |= value1 & 0xffffffffu;
+ break;
+ case 4:
+ value = frvbf_read_mem_SI (current_cpu, pc, address);
+ value = H2T_4 (value);
+ value <<= 32;
+ value1 = frvbf_read_mem_SI (current_cpu, pc, address + 4);
+ value1 = H2T_4 (value1);
+ value |= value1 & 0xffffffffu;
+ break;
+ case 5:
+ value = frvbf_read_mem_DI (current_cpu, pc, address - 3);
+ value = H2T_8 (value);
+ value <<= 24;
+ value1 = frvbf_read_mem_SI (current_cpu, pc, address + 5);
+ value1 = H2T_4 (value1);
+ value |= value1 & 0x00ffffff;
+ break;
+ case 6:
+ value = frvbf_read_mem_DI (current_cpu, pc, address - 2);
+ value = H2T_8 (value);
+ value <<= 16;
+ value1 = frvbf_read_mem_HI (current_cpu, pc, address + 6);
+ value1 = H2T_2 (value1);
+ value |= value1 & 0x0000ffff;
+ break;
+ case 7:
+ value = frvbf_read_mem_DI (current_cpu, pc, address - 1);
+ value = H2T_8 (value);
+ value <<= 8;
+ value1 = frvbf_read_mem_QI (current_cpu, pc, address + 7);
+ value |= value1 & 0x000000ff;
+ break;
+ default:
+ abort (); /* can't happen */
+ }
+ return T2H_8 (value);
+ }
+
DI
frvbf_read_mem_DI (SIM_CPU *current_cpu, IADDR pc, SI address)
{
*************** frvbf_read_mem_DI (SIM_CPU *current_cpu,
*** 394,399 ****
--- 599,611 ----
if (GET_HSR0_DCE (hsr0))
{
int cycles;
+ /* Handle access which crosses cache line boundary */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ {
+ if (DATA_CROSSES_CACHE_LINE (cache, address, 8))
+ return read_mem_unaligned_DI (current_cpu, pc, address);
+ }
cycles = frv_cache_read (cache, 0, address);
if (cycles != 0)
return CACHE_RETURN_DATA (cache, 0, address, DI, 8);
*************** frvbf_read_mem_DF (SIM_CPU *current_cpu,
*** 427,432 ****
--- 639,651 ----
if (GET_HSR0_DCE (hsr0))
{
int cycles;
+ /* Handle access which crosses cache line boundary */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
+ {
+ if (DATA_CROSSES_CACHE_LINE (cache, address, 8))
+ return read_mem_unaligned_DI (current_cpu, pc, address);
+ }
cycles = frv_cache_read (cache, 0, address);
if (cycles != 0)
return CACHE_RETURN_DATA (cache, 0, address, DF, 8);
*************** fr500_check_write_address (SIM_CPU *curr
*** 499,504 ****
--- 718,734 ----
}
static SI
+ fr550_check_write_address (SIM_CPU *current_cpu, SI address, int align_mask)
+ {
+ if ((USI)address >= 0xfe800000 && (USI)address <= 0xfefeffff
+ || (align_mask > 0x3
+ && ((USI)address >= 0xfeff0000 && (USI)address <= 0xfeffffff)))
+ frv_queue_program_interrupt (current_cpu, FRV_DATA_STORE_ERROR);
+
+ return address;
+ }
+
+ static SI
check_write_address (SIM_CPU *current_cpu, SI address, int align_mask)
{
SIM_DESC sd = CPU_STATE (current_cpu);
*************** check_write_address (SIM_CPU *current_cp
*** 512,517 ****
--- 742,750 ----
case bfd_mach_frv:
address = fr500_check_write_address (current_cpu, address, align_mask);
break;
+ case bfd_mach_fr550:
+ address = fr550_check_write_address (current_cpu, address, align_mask);
+ break;
default:
break;
}
*************** frvbf_mem_set_QI (SIM_CPU *current_cpu,
*** 618,623 ****
--- 851,866 ----
frv_cache_write (cache, address, (char *)&value, sizeof (value));
}
+ /* Write a HI which spans two cache lines */
+ static void
+ mem_set_unaligned_HI (SIM_CPU *current_cpu, IADDR pc, SI address, HI value)
+ {
+ FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
+ /* value is already in target byte order */
+ frv_cache_write (cache, address, (char *)&value, 1);
+ frv_cache_write (cache, address + 1, ((char *)&value + 1), 1);
+ }
+
void
frvbf_mem_set_HI (SIM_CPU *current_cpu, IADDR pc, SI address, HI value)
{
*************** frvbf_mem_set_HI (SIM_CPU *current_cpu,
*** 638,644 ****
(char *)&value, sizeof (value));
}
else
! frv_cache_write (cache, address, (char *)&value, sizeof (value));
}
void
--- 881,910 ----
(char *)&value, sizeof (value));
}
else
! {
! /* Handle access which crosses cache line boundary */
! SIM_DESC sd = CPU_STATE (current_cpu);
! if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
! {
! if (DATA_CROSSES_CACHE_LINE (cache, address, 2))
! {
! mem_set_unaligned_HI (current_cpu, pc, address, value);
! return;
! }
! }
! frv_cache_write (cache, address, (char *)&value, sizeof (value));
! }
! }
!
! /* Write a SI which spans two cache lines */
! static void
! mem_set_unaligned_SI (SIM_CPU *current_cpu, IADDR pc, SI address, SI value)
! {
! FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
! unsigned hi_len = cache->line_size - (address & (cache->line_size - 1));
! /* value is already in target byte order */
! frv_cache_write (cache, address, (char *)&value, hi_len);
! frv_cache_write (cache, address + hi_len, (char *)&value + hi_len, 4 - hi_len);
}
void
*************** frvbf_mem_set_SI (SIM_CPU *current_cpu,
*** 661,667 ****
(char *)&value, sizeof (value));
}
else
! frv_cache_write (cache, address, (char *)&value, sizeof (value));
}
void
--- 927,956 ----
(char *)&value, sizeof (value));
}
else
! {
! /* Handle access which crosses cache line boundary */
! SIM_DESC sd = CPU_STATE (current_cpu);
! if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
! {
! if (DATA_CROSSES_CACHE_LINE (cache, address, 4))
! {
! mem_set_unaligned_SI (current_cpu, pc, address, value);
! return;
! }
! }
! frv_cache_write (cache, address, (char *)&value, sizeof (value));
! }
! }
!
! /* Write a DI which spans two cache lines */
! static void
! mem_set_unaligned_DI (SIM_CPU *current_cpu, IADDR pc, SI address, DI value)
! {
! FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
! unsigned hi_len = cache->line_size - (address & (cache->line_size - 1));
! /* value is already in target byte order */
! frv_cache_write (cache, address, (char *)&value, hi_len);
! frv_cache_write (cache, address + hi_len, (char *)&value + hi_len, 8 - hi_len);
}
void
*************** frvbf_mem_set_DI (SIM_CPU *current_cpu,
*** 684,690 ****
(char *)&value, sizeof (value));
}
else
! frv_cache_write (cache, address, (char *)&value, sizeof (value));
}
void
--- 973,991 ----
(char *)&value, sizeof (value));
}
else
! {
! /* Handle access which crosses cache line boundary */
! SIM_DESC sd = CPU_STATE (current_cpu);
! if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
! {
! if (DATA_CROSSES_CACHE_LINE (cache, address, 8))
! {
! mem_set_unaligned_DI (current_cpu, pc, address, value);
! return;
! }
! }
! frv_cache_write (cache, address, (char *)&value, sizeof (value));
! }
}
void
*************** frvbf_mem_set_DF (SIM_CPU *current_cpu,
*** 707,713 ****
(char *)&value, sizeof (value));
}
else
! frv_cache_write (cache, address, (char *)&value, sizeof (value));
}
void
--- 1008,1026 ----
(char *)&value, sizeof (value));
}
else
! {
! /* Handle access which crosses cache line boundary */
! SIM_DESC sd = CPU_STATE (current_cpu);
! if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
! {
! if (DATA_CROSSES_CACHE_LINE (cache, address, 8))
! {
! mem_set_unaligned_DI (current_cpu, pc, address, value);
! return;
! }
! }
! frv_cache_write (cache, address, (char *)&value, sizeof (value));
! }
}
void
Index: sim/frv/mloop.in
===================================================================
RCS file: /cvs/src/src/sim/frv/mloop.in,v
retrieving revision 1.1
diff -c -p -r1.1 mloop.in
*** sim/frv/mloop.in 29 Aug 2003 16:35:46 -0000 1.1
--- sim/frv/mloop.in 6 Oct 2003 20:12:45 -0000
*************** static void
*** 395,400 ****
--- 395,401 ----
break;
case bfd_mach_frvtomcat:
case bfd_mach_fr500:
+ case bfd_mach_fr550:
case bfd_mach_frv:
simulate_dual_insn_prefetch (current_cpu, vpc, 16);
break;
*************** cat <<EOF
*** 454,459 ****
--- 455,461 ----
int first_insn_p = 1;
int last_insn_p = 0;
int ninsns;
+ CGEN_ATTR_VALUE_TYPE slot;
/* If the timer is enabled, then enable model profiling. This is because
the timer needs accurate cycles counts to work properly. */
*************** cat <<EOF
*** 465,470 ****
--- 467,473 ----
vliw = CPU_VLIW (current_cpu);
frv_vliw_reset (vliw, STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach,
CPU_ELF_FLAGS (current_cpu));
+ frv_current_fm_slot = UNIT_NIL;
for (ninsns = 0; ! last_insn_p && ninsns < FRV_VLIW_SIZE; ++ninsns)
{
*************** cat <<EOF
*** 484,489 ****
--- 487,495 ----
if (! error)
frv_vliw_setup_insn (current_cpu, insn);
frv_detect_insn_access_interrupts (current_cpu, sc);
+ slot = (*vliw->current_vliw)[vliw->next_slot - 1];
+ if (slot >= UNIT_FM0 && slot <= UNIT_FM3)
+ frv_current_fm_slot = slot;
vpc = execute (current_cpu, sc, FAST_P);
Index: sim/frv/pipeline.c
===================================================================
RCS file: /cvs/src/src/sim/frv/pipeline.c,v
retrieving revision 1.1
diff -c -p -r1.1 pipeline.c
*** sim/frv/pipeline.c 29 Aug 2003 16:35:46 -0000 1.1
--- sim/frv/pipeline.c 6 Oct 2003 20:12:46 -0000
***************
*** 1,5 ****
/* frv vliw model.
! Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
Contributed by Red Hat.
This file is part of the GNU simulators.
--- 1,5 ----
/* frv vliw model.
! Copyright (C) 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
Contributed by Red Hat.
This file is part of the GNU simulators.
Index: sim/frv/profile.c
===================================================================
RCS file: /cvs/src/src/sim/frv/profile.c,v
retrieving revision 1.4
diff -c -p -r1.4 profile.c
*** sim/frv/profile.c 24 Sep 2003 19:05:39 -0000 1.4
--- sim/frv/profile.c 6 Oct 2003 20:12:46 -0000
*************** with this program; if not, write to the
*** 31,36 ****
--- 31,37 ----
#include "profile.h"
#include "profile-fr400.h"
#include "profile-fr500.h"
+ #include "profile-fr550.h"
static void
reset_gr_flags (SIM_CPU *cpu, INT gr)
*************** update_latencies (SIM_CPU *cpu, int cycl
*** 677,682 ****
--- 678,685 ----
int *fdiv;
int *fsqrt;
int *idiv;
+ int *flt;
+ int *media;
int *ccr;
int *gr = ps->gr_busy;
int *fr = ps->fr_busy;
*************** update_latencies (SIM_CPU *cpu, int cycl
*** 758,763 ****
--- 761,776 ----
++fdiv;
++fsqrt;
}
+ /* Float and media units can occur in 4 slots on some machines. */
+ flt = ps->float_busy;
+ media = ps->media_busy;
+ for (i = 0; i < 4; ++i)
+ {
+ *flt = (*flt <= cycles) ? 0 : (*flt - cycles);
+ *media = (*media <= cycles) ? 0 : (*media - cycles);
+ ++flt;
+ ++media;
+ }
}
/* Print information about the wait for the given number of cycles. */
*************** frvbf_model_insn_before (SIM_CPU *cpu, i
*** 918,923 ****
--- 931,939 ----
case bfd_mach_fr500:
fr500_model_insn_before (cpu, first_p);
break;
+ case bfd_mach_fr550:
+ fr550_model_insn_before (cpu, first_p);
+ break;
default:
break;
}
*************** frvbf_model_insn_after (SIM_CPU *cpu, in
*** 981,986 ****
--- 997,1005 ----
case bfd_mach_fr500:
fr500_model_insn_after (cpu, last_p, cycles);
break;
+ case bfd_mach_fr550:
+ fr550_model_insn_after (cpu, last_p, cycles);
+ break;
default:
break;
}
*************** decrease_ACC_busy (SIM_CPU *cpu, INT out
*** 1242,1248 ****
}
}
- /* start-sanitize-frv */
void
increase_ACC_busy (SIM_CPU *cpu, INT out_ACC, int cycles)
{
--- 1261,1266 ----
*************** enforce_full_acc_latency (SIM_CPU *cpu,
*** 1261,1267 ****
ps->acc_busy_adjust [in_ACC] = -1;
}
- /* end-sanitize-frv */
void
decrease_FR_busy (SIM_CPU *cpu, INT out_FR, int cycles)
{
--- 1279,1284 ----
*************** update_fsqrt_resource_latency (SIM_CPU *
*** 1360,1365 ****
--- 1377,1403 ----
r[in_resource] = cycles;
}
+ /* Set the latency of the given resource to the given number of cycles. */
+ void
+ update_float_resource_latency (SIM_CPU *cpu, INT in_resource, int cycles)
+ {
+ /* operate directly on the busy cycles since each resource can only
+ be used once in a VLIW insn. */
+ FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+ int *r = ps->float_busy;
+ r[in_resource] = cycles;
+ }
+
+ void
+ update_media_resource_latency (SIM_CPU *cpu, INT in_resource, int cycles)
+ {
+ /* operate directly on the busy cycles since each resource can only
+ be used once in a VLIW insn. */
+ FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+ int *r = ps->media_busy;
+ r[in_resource] = cycles;
+ }
+
/* Set the branch penalty to the given number of cycles. */
void
update_branch_penalty (SIM_CPU *cpu, int cycles)
*************** vliw_wait_for_fsqrt_resource (SIM_CPU *c
*** 1572,1577 ****
--- 1610,1655 ----
}
}
+ /* Check the availability of the given float unit resource and update
+ the number of cycles the current VLIW insn must wait until it is available.
+ */
+ void
+ vliw_wait_for_float_resource (SIM_CPU *cpu, INT in_resource)
+ {
+ FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+ int *r = ps->float_busy;
+ /* If the latency of the resource is greater than the current wait
+ then update the current wait. */
+ if (r[in_resource] > ps->vliw_wait)
+ {
+ if (TRACE_INSN_P (cpu))
+ {
+ sprintf (hazard_name, "Resource hazard for floating point unit in slot F%d:", in_resource);
+ }
+ ps->vliw_wait = r[in_resource];
+ }
+ }
+
+ /* Check the availability of the given media unit resource and update
+ the number of cycles the current VLIW insn must wait until it is available.
+ */
+ void
+ vliw_wait_for_media_resource (SIM_CPU *cpu, INT in_resource)
+ {
+ FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+ int *r = ps->media_busy;
+ /* If the latency of the resource is greater than the current wait
+ then update the current wait. */
+ if (r[in_resource] > ps->vliw_wait)
+ {
+ if (TRACE_INSN_P (cpu))
+ {
+ sprintf (hazard_name, "Resource hazard for media unit in slot M%d:", in_resource);
+ }
+ ps->vliw_wait = r[in_resource];
+ }
+ }
+
/* Run the caches until all requests for the given register(s) are satisfied. */
void
load_wait_for_GR (SIM_CPU *cpu, INT in_GR)
*************** post_wait_for_fsqrt (SIM_CPU *cpu, INT s
*** 1824,1829 ****
--- 1902,1943 ----
}
}
+ int
+ post_wait_for_float (SIM_CPU *cpu, INT slot)
+ {
+ FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+ int *flt = ps->float_busy;
+
+ /* Multiple floating point square roots in the same slot need only wait 1
+ extra cycle. */
+ if (flt[slot] > ps->post_wait)
+ {
+ ps->post_wait = flt[slot];
+ if (TRACE_INSN_P (cpu))
+ {
+ sprintf (hazard_name, "Resource hazard for floating point unit in slot F%d:", slot);
+ }
+ }
+ }
+
+ int
+ post_wait_for_media (SIM_CPU *cpu, INT slot)
+ {
+ FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
+ int *media = ps->media_busy;
+
+ /* Multiple floating point square roots in the same slot need only wait 1
+ extra cycle. */
+ if (media[slot] > ps->post_wait)
+ {
+ ps->post_wait = media[slot];
+ if (TRACE_INSN_P (cpu))
+ {
+ sprintf (hazard_name, "Resource hazard for media unit in slot M%d:", slot);
+ }
+ }
+ }
+
/* Print cpu-specific profile information. */
#define COMMAS(n) sim_add_commas (comma_buf, sizeof (comma_buf), (n))
*************** static char *
*** 1863,1870 ****
slot_names[] =
{
"none",
! "I0", "I1", "I01", "IALL",
! "FM0", "FM1", "FM01", "FMALL", "FMLOW",
"B0", "B1", "B01",
"C"
};
--- 1977,1984 ----
slot_names[] =
{
"none",
! "I0", "I1", "I01", "I2", "I3", "IALL",
! "FM0", "FM1", "FM01", "FM2", "FM3", "FMALL", "FMLOW",
"B0", "B1", "B01",
"C"
};
Index: sim/frv/profile.h
===================================================================
RCS file: /cvs/src/src/sim/frv/profile.h,v
retrieving revision 1.3
diff -c -p -r1.3 profile.h
*** sim/frv/profile.h 24 Sep 2003 19:05:39 -0000 1.3
--- sim/frv/profile.h 6 Oct 2003 20:12:46 -0000
*************** typedef struct
*** 45,50 ****
--- 45,52 ----
int idiv_busy[2]; /* Cycles until integer division unit is available. */
int fdiv_busy[2]; /* Cycles until float division unit is available. */
int fsqrt_busy[2]; /* Cycles until square root unit is available. */
+ int float_busy[4]; /* Cycles until floating point unit is available. */
+ int media_busy[4]; /* Cycles until media unit is available. */
int branch_penalty; /* Cycles until branch is complete. */
int gr_latency[64]; /* Cycles until target GR is available. */
*************** typedef struct
*** 72,77 ****
--- 74,81 ----
int branch_hint; /* hint field from branch insn. */
USI branch_address; /* Address of predicted branch. */
USI insn_fetch_address;/* Address of sequential insns fetched. */
+ int mclracc_acc; /* ACC number of register cleared by mclracc. */
+ int mclracc_A; /* A field of mclracc. */
/* We need to know when the first branch of a vliw insn is taken, so that
we don't consider the remaining branches in the vliw insn. */
*************** void decrease_ACC_busy (SIM_CPU *, INT,
*** 117,128 ****
--- 121,135 ----
void decrease_FR_busy (SIM_CPU *, INT, int);
void decrease_GR_busy (SIM_CPU *, INT, int);
void increase_FR_busy (SIM_CPU *, INT, int);
+ void increase_ACC_busy (SIM_CPU *, INT, int);
void update_ACC_latency (SIM_CPU *, INT, int);
void update_CCR_latency (SIM_CPU *, INT, int);
void update_SPR_latency (SIM_CPU *, INT, int);
void update_idiv_resource_latency (SIM_CPU *, INT, int);
void update_fdiv_resource_latency (SIM_CPU *, INT, int);
void update_fsqrt_resource_latency (SIM_CPU *, INT, int);
+ void update_float_resource_latency (SIM_CPU *, INT, int);
+ void update_media_resource_latency (SIM_CPU *, INT, int);
void update_branch_penalty (SIM_CPU *, int);
void update_ACC_ptime (SIM_CPU *, INT, int);
void update_SPR_ptime (SIM_CPU *, INT, int);
*************** void vliw_wait_for_SPR (SIM_CPU *, INT);
*** 136,146 ****
--- 143,156 ----
void vliw_wait_for_idiv_resource (SIM_CPU *, INT);
void vliw_wait_for_fdiv_resource (SIM_CPU *, INT);
void vliw_wait_for_fsqrt_resource (SIM_CPU *, INT);
+ void vliw_wait_for_float_resource (SIM_CPU *, INT);
+ void vliw_wait_for_media_resource (SIM_CPU *, INT);
void load_wait_for_GR (SIM_CPU *, INT);
void load_wait_for_FR (SIM_CPU *, INT);
void load_wait_for_GRdouble (SIM_CPU *, INT);
void load_wait_for_FRdouble (SIM_CPU *, INT);
void enforce_full_fr_latency (SIM_CPU *, INT);
+ void enforce_full_acc_latency (SIM_CPU *, INT);
int post_wait_for_FR (SIM_CPU *, INT);
int post_wait_for_FRdouble (SIM_CPU *, INT);
int post_wait_for_ACC (SIM_CPU *, INT);
*************** int post_wait_for_CCR (SIM_CPU *, INT);
*** 148,153 ****
--- 158,165 ----
int post_wait_for_SPR (SIM_CPU *, INT);
int post_wait_for_fdiv (SIM_CPU *, INT);
int post_wait_for_fsqrt (SIM_CPU *, INT);
+ int post_wait_for_float (SIM_CPU *, INT);
+ int post_wait_for_media (SIM_CPU *, INT);
void trace_vliw_wait_cycles (SIM_CPU *);
void handle_resource_wait (SIM_CPU *);
Index: sim/frv/registers.c
===================================================================
RCS file: /cvs/src/src/sim/frv/registers.c,v
retrieving revision 1.2
diff -c -p -r1.2 registers.c
*** sim/frv/registers.c 12 Sep 2003 22:05:22 -0000 1.2
--- sim/frv/registers.c 6 Oct 2003 20:12:46 -0000
*************** static FRV_SPR_CONTROL_INFO frv_spr[] =
*** 165,174 ****
{0x00000000, 0x00000000, 0x00000000, 0x00000003, IMPL, USER}, /* LR */
{0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* LCR */
! /* spr registers 274-287 are reserved */
RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED,
{0xe0000021, 0x20000000, 0xe0000000, 0xffffffc2, IMPL, USER}, /* ISR */
--- 165,177 ----
{0x00000000, 0x00000000, 0x00000000, 0x00000003, IMPL, USER}, /* LR */
{0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* LCR */
! /* spr registers 274-279 and 282-287 are reserved. */
! /* spr registers 280 and 281 are iacc0h and iacc0l (fr405). */
RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0H */
! {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0L */
! RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED,
{0xe0000021, 0x20000000, 0xe0000000, 0xffffffc2, IMPL, USER}, /* ISR */
*************** static FRV_SPR_CONTROL_INFO fr500_spr[]
*** 3055,3065 ****
RESERVED
};
! /* SPR definitions for the fr400 machine.
! See the FR400 LSI for implementation details. */
! static FRV_SPR_CONTROL_INFO fr400_spr[] =
{
! {0x200030fe, 0x200030fc, 0xf00030fd, 0xffffff80, IMPL, SUP}, /* PSR */
{0x00000000, 0x00000000, 0x00000003, 0x00000003, IMPL, SUP}, /* PCSR */
{0x00000000, 0x00000000, 0xffffffff, 0x00000003, IMPL, SUP}, /* BPCSR */
{0x00000000, 0x00000000, 0x0000000f, 0x000007ff, IMPL, SUP}, /* TBR */
--- 3058,3068 ----
RESERVED
};
! /* SPR definitions for the fr550 machine.
! See the FR550 LSI for implementation details. */
! static FRV_SPR_CONTROL_INFO fr550_spr[] =
{
! {0x3000107e, 0x3000107c, 0xff0071fd, 0xffff9e00, IMPL, SUP}, /* PSR */
{0x00000000, 0x00000000, 0x00000003, 0x00000003, IMPL, SUP}, /* PCSR */
{0x00000000, 0x00000000, 0xffffffff, 0x00000003, IMPL, SUP}, /* BPCSR */
{0x00000000, 0x00000000, 0x0000000f, 0x000007ff, IMPL, SUP}, /* TBR */
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3070,3078 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED,
! {0x00000d40, 0x00000d40, 0xcc400fc0, 0x317feff8, IMPL, SUP}, /* HSR0 */
! /* HSR1-63 are unimplemented on the fr400. */
RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
--- 3073,3081 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED,
! {0x000003c0, 0x00000000, 0xce000c00, 0x313fec38, IMPL, SUP}, /* HSR0 */
! /* HSR1-63 are unimplemented on the fr550. */
RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3147,3153 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED,
! {0x20000021, 0x20000000, 0xa0000000, 0xffffffc2, IMPL, USER}, /* ISR */
/* spr registers 289-351 are reserved */
RESERVED,
--- 3150,3156 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED,
! {0x20000030, 0x20000000, 0xa0000000, 0xffffffd3, IMPL, USER}, /* ISR */
/* spr registers 289-351 are reserved */
RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3165,3171 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED,
! /* NEEAR0-31 are unimplemented on the fr400. */
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
--- 3168,3174 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED,
! /* NEEAR0-31 are unimplemented on the fr550. */
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3174,3180 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED,
! /* NESR0-31 are unimplemented on the fr400. */
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
--- 3177,3183 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED,
! /* NESR0-31 are unimplemented on the fr550. */
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3183,3189 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED,
! /* NECR is unimplemented on the fr400. */
RESERVED,
/* spr registers 417-431 are reserved */
--- 3186,3192 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED,
! /* NECR is unimplemented on the fr550. */
RESERVED,
/* spr registers 417-431 are reserved */
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3192,3199 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED,
! /* GNER0, GNER1, FNER0, FNER1 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED,
/* spr registers 436-511 are reserved */
RESERVED, RESERVED, RESERVED, RESERVED,
--- 3195,3204 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED,
! {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* GNER0 */
! {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* GNER1 */
! {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* FNER0 */
! {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* FNER1 */
/* spr registers 436-511 are reserved */
RESERVED, RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3214,3221 ****
RESERVED, RESERVED,
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR0 */
! /* EPCR1-63 are unimplemented on the fr400. */
RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
--- 3219,3234 ----
RESERVED, RESERVED,
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR0 */
+ RESERVED,
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR2 */
! /* EPCR3-7 are unimplemented on the fr550. */
! RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED,
!
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR8 */
!
! /* EPCR9-63 are unimplemented on the fr550. */
RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3227,3246 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED,
{0x00000100, 0x00000100, 0x00000100, 0xffffffff, IMPL, SUP}, /* ESR0 */
! /* ESR1-13 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR14 */
! {0x00000800, 0x00000800, 0x00000800, 0xffffffff, IMPL, SUP},
! /* ESR16-63 are unimplemented on the fr400. */
RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
--- 3240,3265 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED,
{0x00000100, 0x00000100, 0x00000100, 0xffffffff, IMPL, SUP}, /* ESR0 */
+ RESERVED,
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR2 */
! /* ESR3-7 are unimplemented on the fr550. */
! RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED,
!
! {0x00000200, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR8 */
!
! /* ESR9-13 are unimplemented on the fr550. */
! RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR14 */
! {0x00000020, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
! /* ESR16-63 are unimplemented on the fr550. */
RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3252,3258 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
! /* EIR0-31 are unimplemented on the fr400. */
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
--- 3271,3277 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
! /* EIR0-31 are unimplemented on the fr550. */
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3261,3269 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED,
! /* ESFR0 is unimplemented on the fr400. */
RESERVED,
-
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESFR1 */
/* spr registers 674-767 are reserved */
--- 3280,3287 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED,
! /* ESFR0 is unimplemented on the fr550. */
RESERVED,
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESFR1 */
/* spr registers 674-767 are reserved */
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3288,3294 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED,
! /* SR0-3 ARE unimplemented on the fr400. */
RESERVED, RESERVED, RESERVED, RESERVED,
/* spr registers 772-1023 are reserved */
--- 3306,3312 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED,
! /* SR0-SR3 are unimplemented on the fr550. */
RESERVED, RESERVED, RESERVED, RESERVED,
/* spr registers 772-1023 are reserved */
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3344,3350 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
! /* FSR0-63 are unimplemented on the fr400. */
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
--- 3362,3370 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
! {0x00800000, 0x00800000, 0xc0e00000, 0xc0fe03ff, IMPL, USER}, /* FSR0 */
!
! /* FSR1-63 are unimplemented on the fr550. */
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3357,3366 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED,
! /* FQ0-31 are unimplemented on the fr400. */
/* Each FQ register is a pair of 32 bit registers. */
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
--- 3377,3387 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED,
! /* FQ0-31 are unimplemented on the fr550. */
/* Each FQ register is a pair of 32 bit registers. */
+ RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3373,3379 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED,
/* spr registers 1152-1271 are reserved */
RESERVED, RESERVED, RESERVED,
--- 3394,3400 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED,
/* spr registers 1152-1271 are reserved */
RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3402,3419 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED,
! /* MCILR0-1 are unimplemented on the fr400. */
RESERVED, RESERVED,
/* spr registers 1274-1279 are reserved */
RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! {0x00000000, 0x00000000, 0x01c00000, 0x0fff8fc0, IMPL, USER}, /* MSR0 */
! {0x00000000, 0x00000000, 0x00000000, 0xffffffcd, IMPL, USER},
! /* MSR2-63 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
--- 3423,3439 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED,
! /* MCILR0-1 are unimplemented on the fr550. */
RESERVED, RESERVED,
/* spr registers 1274-1279 are reserved */
RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! {0x00001002, 0x00000000, 0x01e00000, 0x07ffffc2, IMPL, USER}, /* MSR0 */
! /* MSR1-63 are unimplemented on the fr550. */
! RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3427,3433 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
! /* MQ0-31 are unimplemented on the fr400. */
/* Each MQ register is a pair of 32 bit registers. */
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
--- 3447,3453 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
! /* MQ0-31 are unimplemented on the fr550. */
/* Each MQ register is a pair of 32 bit registers. */
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3449,3458 ****
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
! /* ACC4-63 are unimplemented on the fr400. */
! RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
--- 3469,3481 ----
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC7 */
! /* ACC8-63 are unimplemented on the fr550. */
! RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3471,3480 ****
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
! /* ACCG4-63 are unimplemented on the fr400. */
! RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
--- 3494,3506 ----
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG7 */
! /* ACCG8-63 are unimplemented on the fr550. */
! RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3487,3500 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
! /* EAR0-14 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR15 */
! /* EAR16-63 are unimplemented on the fr400. */
RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
--- 3513,3531 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
! /* EAR0-7 are unimplemented on the fr550. */
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR8 */
+
+ /* EAR9-14 are unimplemented on the fr550. */
+ RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR15 */
! /* EAR16-63 are unimplemented on the fr550. */
RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3506,3512 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
! /* EDR0-63 are unimplemented on the fr400. */
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
--- 3537,3543 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
! /* EDR0-63 are unimplemented on the fr550. */
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3521,3531 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
! /* IAMLR0-63 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
--- 3552,3576 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* IAMLR0 */
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* IAMLR8 */
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* IAMLR15 */
!
! /* IAMLR16-63 are unimplemented on the fr550. */
! RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3536,3554 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
! {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP}, /* IAMPR0 */
! {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP}, /* IAMPR7 */
! /* IAMPR08-63 are unimplemented on the fr400. */
! RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
--- 3581,3605 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* IAMPR0 */
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* IAMPR8 */
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* IAMPR15 */
! /* IAMPR16-63 are unimplemented on the fr550. */
! RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3559,3569 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
! /* DAMLR0-63 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
--- 3610,3634 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* DAMLR0 */
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* DAMLR8 */
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fffff, IMPL, SUP}, /* DAMLR15 */
!
! /* DAMLR16-63 are unimplemented on the fr550. */
! RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3574,3592 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
! {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP}, /* DAMPR0 */
! {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP}, /* DAMPR7 */
! /* DAMPR08-63 are unimplemented on the fr400. */
! RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
--- 3639,3663 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* DAMPR0 */
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* DAMPR8 */
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff00, IMPL, SUP}, /* DAMPR15 */
! /* DAMPR16-63 are unimplemented on the fr550. */
! RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3597,3605 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
! {0x00000808, 0x00000808, 0x00000808, 0xffffffff, IMPL, SUP}, /* AMCR */
! /* STBAR, MMCR not implemented on the fr400. */
RESERVED, RESERVED,
/* spr registers 1923-2047 are reserved */
--- 3668,3676 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED,
! {0x00001010, 0x00001010, 0x0000ffff, 0xffffffff, IMPL, SUP}, /* AMCR */
! /* STBAR, MMCR not implemented on the fr550. */
RESERVED, RESERVED,
/* spr registers 1923-2047 are reserved */
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 3643,3697 ****
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBAR0 */
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
!
! /* DBAR2-3 not implemented on the fr400. */
! RESERVED, RESERVED,
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR00 */
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
! /* DBDR02-03 are unimplemented on the fr400. */
RESERVED, RESERVED,
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR10 */
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
! /* DBDR12-13 are unimplemented on the fr400. */
RESERVED, RESERVED,
! /* DBDR20-23 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED,
! /* DBDR30-33 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED,
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR00 */
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
! /* DBMR02-03 are unimplemented on the fr400. */
RESERVED, RESERVED,
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR10 */
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
! /* DBMR12-13 are unimplemented on the fr400. */
RESERVED, RESERVED,
! /* DBMR20-23 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED,
! /* DBMR30-33 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED,
! /* CPCFR, CPCR and CPSR are unimplemented on the fr400. */
RESERVED, RESERVED, RESERVED,
RESERVED, /* spr register 2095 */
! /* CPESR0-1 are unimplemented on the fr400. */
RESERVED, RESERVED,
! /* CPEMR0-1 are unimplemented on the fr400. */
RESERVED, RESERVED,
/* spr registers 2100-2199 are reserved */
--- 3714,3779 ----
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBAR0 */
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBAR3 */
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR00 */
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
! /* DBDR02-03 are unimplemented on the fr550. */
RESERVED, RESERVED,
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR10 */
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
! /* DBDR12-13 are unimplemented on the fr550. */
RESERVED, RESERVED,
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR20 */
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
! /* DBDR22-23 are unimplemented on the fr550. */
! RESERVED, RESERVED,
!
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR30 */
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
!
! /* DBDR32-33 are unimplemented on the fr550. */
! RESERVED, RESERVED,
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR00 */
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
! /* DBMR02-03 are unimplemented on the fr550. */
RESERVED, RESERVED,
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR10 */
{0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
! /* DBMR12-13 are unimplemented on the fr550. */
RESERVED, RESERVED,
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR20 */
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
! /* DBMR22-23 are unimplemented on the fr550. */
! RESERVED, RESERVED,
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR30 */
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
!
! /* DBMR32-33 are unimplemented on the fr550. */
! RESERVED, RESERVED,
!
! /* CPCFR, CPCR and CPSR are unimplemented on the fr550. */
RESERVED, RESERVED, RESERVED,
RESERVED, /* spr register 2095 */
! /* CPESR0-1 are unimplemented on the fr550. */
RESERVED, RESERVED,
! /* CPEMR0-1 are unimplemented on the fr550. */
RESERVED, RESERVED,
/* spr registers 2100-2199 are reserved */
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 4068,4075 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! /* spr registers 3800-3899 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
--- 4150,4156 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! /* spr registers 3800-3847 are reserved */
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 4079,4084 ****
--- 4160,4171 ----
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED,
+
+ {0x00000001, 0x00000000, 0x00000000, 0xffff88fd, IMPL, SUP}, /* IHSR8 */
+
+ /* spr registers 3849-4095 are reserved */
+ RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 4089,4096 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
-
- /* spr registers 3900-3999 are reserved */
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
--- 4176,4181 ----
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 4111,4118 ****
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
-
- /* spr registers 4000-4095 are reserved */
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
--- 4196,4201 ----
*************** static FRV_SPR_CONTROL_INFO fr400_spr[]
*** 4135,4156 ****
RESERVED
};
! /* Initialize register control for this cpu */
! void
! frv_register_control_init (SIM_CPU *cpu)
{
! FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (cpu);
! SIM_DESC sd = CPU_STATE (cpu);
! int mach = STATE_ARCHITECTURE (sd)->mach;
! if (sizeof (fr400_spr) != FRV_MAX_SPR * sizeof (*fr400_spr))
! abort ();
! if (sizeof (fr500_spr) != FRV_MAX_SPR * sizeof (*fr500_spr))
! abort ();
! if (sizeof (frv_spr) != FRV_MAX_SPR * sizeof (*frv_spr))
! abort ();
! switch (mach)
{
case bfd_mach_frvtomcat:
case bfd_mach_fr500:
--- 4218,5324 ----
RESERVED
};
! /* SPR definitions for the fr400 machine.
! See the FR400 LSI for implementation details. */
! static FRV_SPR_CONTROL_INFO fr400_spr[] =
{
! {0x200030fe, 0x200030fc, 0xf00030fd, 0xffffff80, IMPL, SUP}, /* PSR */
! {0x00000000, 0x00000000, 0x00000003, 0x00000003, IMPL, SUP}, /* PCSR */
! {0x00000000, 0x00000000, 0xffffffff, 0x00000003, IMPL, SUP}, /* BPCSR */
! {0x00000000, 0x00000000, 0x0000000f, 0x000007ff, IMPL, SUP}, /* TBR */
! {0x00000000, 0x00000000, 0x00000000, 0xffffeffe, IMPL, SUP}, /* BPSR */
! /* spr registers 5-15 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED,
! {0x00000d40, 0x00000d40, 0xcc400fc0, 0x317feff8, IMPL, SUP}, /* HSR0 */
!
! /* HSR1-63 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 80-255 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED,
!
! {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* CCR */
!
! /* spr registers 257-262 are reserved */
! RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED,
!
! {0x00000000, 0x00000000, 0x00000000, 0xffff0000, IMPL, USER}, /* CCCR */
!
! /* spr registers 264-271 are reserved */
! RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED,
!
! {0x00000000, 0x00000000, 0x00000003, 0x00000003, IMPL, USER}, /* LR */
! {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* LCR */
!
! /* spr registers 274-279 and 282-287 are reserved. */
! /* spr registers 280 and 281 are iacc0h and iacc0l (fr405). */
! RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0H */
! {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0L */
! RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED,
!
! {0x20000021, 0x20000000, 0xa0000000, 0xffffffc2, IMPL, USER}, /* ISR */
!
! /* spr registers 289-351 are reserved */
! RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED,
!
! /* NEEAR0-31 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED,
!
! /* NESR0-31 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED,
!
! /* NECR is unimplemented on the fr400. */
! RESERVED,
!
! /* spr registers 417-431 are reserved */
! RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED,
!
! /* GNER0, GNER1, FNER0, FNER1 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 436-511 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED,
!
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR0 */
!
! /* EPCR1-63 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! {0x00000100, 0x00000100, 0x00000100, 0xffffffff, IMPL, SUP}, /* ESR0 */
!
! /* ESR1-13 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR14 */
! {0x00000800, 0x00000800, 0x00000800, 0xffffffff, IMPL, SUP},
!
! /* ESR16-63 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* EIR0-31 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED,
!
! /* ESFR0 is unimplemented on the fr400. */
! RESERVED,
!
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESFR1 */
!
! /* spr registers 674-767 are reserved */
! RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED,
!
! /* SR0-3 ARE unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 772-1023 are reserved */
! RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* FSR0-63 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* FQ0-31 are unimplemented on the fr400. */
! /* Each FQ register is a pair of 32 bit registers. */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 1152-1271 are reserved */
! RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED,
!
! /* MCILR0-1 are unimplemented on the fr400. */
! RESERVED, RESERVED,
!
! /* spr registers 1274-1279 are reserved */
! RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
!
! {0x00000000, 0x00000000, 0x01c00000, 0x0fff8fc0, IMPL, USER}, /* MSR0 */
! {0x00000000, 0x00000000, 0x00000000, 0xffffffcd, IMPL, USER},
!
! /* MSR2-63 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* MQ0-31 are unimplemented on the fr400. */
! /* Each MQ register is a pair of 32 bit registers. */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* Accumulators are read-only by the user except for special
! insns and side effect of other insns. */
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC0 */
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
!
! /* ACC4-63 are unimplemented on the fr400. */
! RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* Accumulator guards are read-only by the user except for special
! insns and side effect of other insns. */
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG0 */
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
!
! /* ACCG4-63 are unimplemented on the fr400. */
! RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* EAR0-14 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
!
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR15 */
!
! /* EAR16-63 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* EDR0-63 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* IAMLR0-63 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP}, /* IAMPR0 */
! {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0x000fff02, IMPL, SUP}, /* IAMPR7 */
!
! /* IAMPR08-63 are unimplemented on the fr400. */
! RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* DAMLR0-63 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP}, /* DAMPR0 */
! {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000001, 0x000fff00, IMPL, SUP}, /* DAMPR7 */
!
! /* DAMPR08-63 are unimplemented on the fr400. */
! RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! {0x00000808, 0x00000808, 0x00000808, 0xffffffff, IMPL, SUP}, /* AMCR */
!
! /* STBAR, MMCR not implemented on the fr400. */
! RESERVED, RESERVED,
!
! /* spr registers 1923-2047 are reserved */
! RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED,
!
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DCR */
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* BRR */
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* NMAR */
!
! RESERVED, /* spr register 2051 */
!
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IBAR0 */
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IBAR3 */
!
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBAR0 */
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
!
! /* DBAR2-3 not implemented on the fr400. */
! RESERVED, RESERVED,
!
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR00 */
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
!
! /* DBDR02-03 are unimplemented on the fr400. */
! RESERVED, RESERVED,
!
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR10 */
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
!
! /* DBDR12-13 are unimplemented on the fr400. */
! RESERVED, RESERVED,
!
! /* DBDR20-23 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* DBDR30-33 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR00 */
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
!
! /* DBMR02-03 are unimplemented on the fr400. */
! RESERVED, RESERVED,
!
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR10 */
! {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
!
! /* DBMR12-13 are unimplemented on the fr400. */
! RESERVED, RESERVED,
!
! /* DBMR20-23 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* DBMR30-33 are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* CPCFR, CPCR and CPSR are unimplemented on the fr400. */
! RESERVED, RESERVED, RESERVED,
!
! RESERVED, /* spr register 2095 */
!
! /* CPESR0-1 are unimplemented on the fr400. */
! RESERVED, RESERVED,
!
! /* CPEMR0-1 are unimplemented on the fr400. */
! RESERVED, RESERVED,
!
! /* spr registers 2100-2199 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 2200-2299 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 2300-2399 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 2400-2499 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 2500-2599 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 2600-2699 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 2700-2799 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 2800-2899 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 2900-2999 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 3000-3099 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 3100-3199 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 3200-3299 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 3300-3399 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 3400-3499 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 3500-3599 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 3600-3699 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 3700-3799 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 3800-3899 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 3900-3999 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
!
! /* spr registers 4000-4095 are reserved */
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
! RESERVED
! };
!
! /* Initialize register control for this cpu */
! void
! frv_register_control_init (SIM_CPU *cpu)
! {
! FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (cpu);
! SIM_DESC sd = CPU_STATE (cpu);
! int mach = STATE_ARCHITECTURE (sd)->mach;
!
! if (sizeof (fr400_spr) != FRV_MAX_SPR * sizeof (*fr400_spr))
! abort ();
! if (sizeof (fr500_spr) != FRV_MAX_SPR * sizeof (*fr500_spr))
! abort ();
! if (sizeof (fr550_spr) != FRV_MAX_SPR * sizeof (*fr550_spr))
! abort ();
! if (sizeof (frv_spr) != FRV_MAX_SPR * sizeof (*frv_spr))
! abort ();
!
! switch (mach)
{
case bfd_mach_frvtomcat:
case bfd_mach_fr500:
*************** frv_register_control_init (SIM_CPU *cpu)
*** 4158,4163 ****
--- 5326,5336 ----
control->cpr = 0;
control->spr = fr500_spr;
return;
+ case bfd_mach_fr550:
+ control->fr = 1;
+ control->cpr = 0;
+ control->spr = fr550_spr;
+ return;
case bfd_mach_fr400:
control->fr = 1;
control->cpr = 0;
*************** frv_check_spr_read_access (SIM_CPU *curr
*** 4273,4292 ****
if (! control->spr[spr].implemented)
{
SIM_DESC sd = CPU_STATE (current_cpu);
! if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
{
/* On the fr400: if this is an unimplemented accumulator, then
generate an illegal_instruction_interrupt, otherwise no interrupt.
*/
if (spr >= H_SPR_ACC4 && spr <= H_SPR_ACC63
|| spr >= H_SPR_ACCG4 && spr <= H_SPR_ACCG63)
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
! }
! else
! {
! /* On other machines, it's a register_exception. */
! frv_queue_register_exception_interrupt (current_cpu,
! FRV_REC_UNIMPLEMENTED);
}
}
}
--- 5446,5467 ----
if (! control->spr[spr].implemented)
{
SIM_DESC sd = CPU_STATE (current_cpu);
! switch (STATE_ARCHITECTURE (sd)->mach)
{
+ case bfd_mach_fr400:
/* On the fr400: if this is an unimplemented accumulator, then
generate an illegal_instruction_interrupt, otherwise no interrupt.
*/
if (spr >= H_SPR_ACC4 && spr <= H_SPR_ACC63
|| spr >= H_SPR_ACCG4 && spr <= H_SPR_ACCG63)
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
! break;
! case bfd_mach_fr550:
! /* No interrupt on the fr550 */
! break;
! default:
! frv_queue_register_exception_interrupt (current_cpu, FRV_REC_UNIMPLEMENTED);
! break;
}
}
}
*************** frv_check_register_access (
*** 4364,4379 ****
/* The register is not available. Generate an exception. */
sd = CPU_STATE (current_cpu);
! if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
{
! /* On the fr400 this generates an illegal_instruction interrupt. */
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
! }
! else
! {
/* On other machines, it's a register_exception. */
! frv_queue_register_exception_interrupt (current_cpu,
! FRV_REC_UNIMPLEMENTED);
}
return 0;
}
--- 5539,5555 ----
/* The register is not available. Generate an exception. */
sd = CPU_STATE (current_cpu);
! switch (STATE_ARCHITECTURE (sd)->mach)
{
! case bfd_mach_fr400:
! case bfd_mach_fr550:
! /* On some machines this generates an illegal_instruction interrupt. */
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
! break;
! default:
/* On other machines, it's a register_exception. */
! frv_queue_register_exception_interrupt (current_cpu, FRV_REC_UNIMPLEMENTED);
! break;
}
return 0;
}
Index: sim/frv/traps.c
===================================================================
RCS file: /cvs/src/src/sim/frv/traps.c,v
retrieving revision 1.1
diff -c -p -r1.1 traps.c
*** sim/frv/traps.c 29 Aug 2003 16:35:47 -0000 1.1
--- sim/frv/traps.c 6 Oct 2003 20:12:47 -0000
***************
*** 1,5 ****
/* frv trap support
! Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
Contributed by Red Hat.
This file is part of the GNU simulators.
--- 1,5 ----
/* frv trap support
! Copyright (C) 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
Contributed by Red Hat.
This file is part of the GNU simulators.
*************** with this program; if not, write to the
*** 30,35 ****
--- 30,37 ----
#include "bfd.h"
#include "libiberty.h"
+ CGEN_ATTR_VALUE_TYPE frv_current_fm_slot;
+
/* The semantic code invokes this for invalid (unrecognized) instructions. */
SEM_PC
*************** frv_itrap (SIM_CPU *current_cpu, PCADDR
*** 276,284 ****
void
frv_mtrap (SIM_CPU *current_cpu)
{
/* Check the status of media exceptions in MSR0. */
SI msr = GET_MSR (0);
! if (GET_MSR_AOVF (msr) || GET_MSR_MTT (msr))
frv_queue_program_interrupt (current_cpu, FRV_MP_EXCEPTION);
}
--- 278,288 ----
void
frv_mtrap (SIM_CPU *current_cpu)
{
+ SIM_DESC sd = CPU_STATE (current_cpu);
+
/* Check the status of media exceptions in MSR0. */
SI msr = GET_MSR (0);
! if (GET_MSR_AOVF (msr) || GET_MSR_MTT (msr) && STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
frv_queue_program_interrupt (current_cpu, FRV_MP_EXCEPTION);
}
*************** frvbf_media_cr_not_aligned (SIM_CPU *cur
*** 584,594 ****
{
SIM_DESC sd = CPU_STATE (current_cpu);
! /* On the fr400 this generates an illegal_instruction interrupt. */
! if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
! frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
! else
! frv_set_mp_exception_registers (current_cpu, MTT_CR_NOT_ALIGNED, 0);
}
/* Record state for media exception: media_acc_not_aligned. */
--- 588,604 ----
{
SIM_DESC sd = CPU_STATE (current_cpu);
! /* On some machines this generates an illegal_instruction interrupt. */
! switch (STATE_ARCHITECTURE (sd)->mach)
! {
! case bfd_mach_fr400:
! case bfd_mach_fr550:
! frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
! break;
! default:
! frv_set_mp_exception_registers (current_cpu, MTT_CR_NOT_ALIGNED, 0);
! break;
! }
}
/* Record state for media exception: media_acc_not_aligned. */
*************** frvbf_media_acc_not_aligned (SIM_CPU *cu
*** 597,607 ****
{
SIM_DESC sd = CPU_STATE (current_cpu);
! /* On the fr400 this generates an illegal_instruction interrupt. */
! if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
! frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
! else
! frv_set_mp_exception_registers (current_cpu, MTT_ACC_NOT_ALIGNED, 0);
}
/* Record state for media exception: media_register_not_aligned. */
--- 607,623 ----
{
SIM_DESC sd = CPU_STATE (current_cpu);
! /* On some machines this generates an illegal_instruction interrupt. */
! switch (STATE_ARCHITECTURE (sd)->mach)
! {
! case bfd_mach_fr400:
! case bfd_mach_fr550:
! frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
! break;
! default:
! frv_set_mp_exception_registers (current_cpu, MTT_ACC_NOT_ALIGNED, 0);
! break;
! }
}
/* Record state for media exception: media_register_not_aligned. */
*************** frvbf_media_register_not_aligned (SIM_CP
*** 610,620 ****
{
SIM_DESC sd = CPU_STATE (current_cpu);
! /* On the fr400 this generates an illegal_instruction interrupt. */
! if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
! frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
! else
! frv_set_mp_exception_registers (current_cpu, MTT_INVALID_FR, 0);
}
/* Record state for media exception: media_overflow. */
--- 626,642 ----
{
SIM_DESC sd = CPU_STATE (current_cpu);
! /* On some machines this generates an illegal_instruction interrupt. */
! switch (STATE_ARCHITECTURE (sd)->mach)
! {
! case bfd_mach_fr400:
! case bfd_mach_fr550:
! frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
! break;
! default:
! frv_set_mp_exception_registers (current_cpu, MTT_INVALID_FR, 0);
! break;
! }
}
/* Record state for media exception: media_overflow. */
*************** frvbf_check_recovering_store (
*** 723,728 ****
--- 745,794 ----
break; /* Only consider the first matching register. */
}
} /* loop over active neear registers. */
+ }
+
+ SI
+ frvbf_check_acc_range (SIM_CPU *current_cpu, SI regno)
+ {
+ /* Only applicable to fr550 */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
+ return;
+
+ /* On the fr550, media insns in slots 0 and 2 can only access
+ accumulators acc0-acc3. Insns in slots 1 and 3 can only access
+ accumulators acc4-acc7 */
+ switch (frv_current_fm_slot)
+ {
+ case UNIT_FM0:
+ case UNIT_FM2:
+ if (regno <= 3)
+ return 1; /* all is ok */
+ break;
+ case UNIT_FM1:
+ case UNIT_FM3:
+ if (regno >= 4)
+ return 1; /* all is ok */
+ break;
+ }
+
+ /* The specified accumulator is out of range. Queue an illegal_instruction
+ interrupt. */
+ frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
+ return 0;
+ }
+
+ void
+ frvbf_check_swap_address (SIM_CPU *current_cpu, SI address)
+ {
+ /* Only applicable to fr550 */
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
+ return;
+
+ /* Adress must be aligned on a word boundary. */
+ if (address & 0x3)
+ frv_queue_data_access_exception_interrupt (current_cpu);
}
static void