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[PATCH] sim: bfin: add missing VS set with add/sub insns


From: Robin Getz <robin.getz@analog.com>

The 16bit add/sub insns missed setting the VS bit in ASTAT whenever the
V bit was also set.

Committed.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

2011-03-26  Robin Getz  <robin.getz@analog.com>

	* bfin-sim.c (decode_dsp32alu_0): Set VS when V is set.
---
 sim/bfin/bfin-sim.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c
index ef84025..2e9c760 100644
--- a/sim/bfin/bfin-sim.c
+++ b/sim/bfin/bfin-sim.c
@@ -4144,6 +4144,9 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
 
       SET_ASTATREG (ac0, ac0_i);
       SET_ASTATREG (v, v_i);
+      if (v_i)
+	SET_ASTATREG (vs, v_i);
+
       if (HL)
 	SET_DREG_H (dst0, val << 16);
       else
-- 
1.7.4.1


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