This is the mail archive of the gdb-patches@sourceware.org mailing list for the GDB project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [try 2nd 5/8] Displaced stepping for Thumb 32-bit insns


On 05/18/2011 01:14 AM, Ulrich Weigand wrote:
>> > +static int
>> > +thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1,
>> > +			      uint16_t insn2, struct regcache *regs,
>> > +			      struct displaced_step_closure *dsc)
>> > +{
>> > +  unsigned int rn = bits (insn1, 0, 3);
>> > +
>> > +  if (rn == ARM_PC_REGNUM)
>> > +    return thumb_copy_unmodified_32bit (gdbarch, insn1, insn2,
>> > +					"copro load/store", dsc);
>> > +
>> > +  if (debug_displaced)
>> > +    fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
>> > +			"load/store insn %.4x%.4x\n", insn1, insn2);
>> > +
>> > +  dsc->modinsn[0] = insn1 & 0xfff0;
>> > +  dsc->modinsn[1] = insn2;
>> > +  dsc->numinsns = 2;
> This doesn't look right: you're replacing the RN register if it is anything
> *but* 15 -- but those cases do not need to be replaced!
> 

Sorry, the condition check should be reversed.

> In fact, unless I'm missing something, in Thumb mode no coprocessor
> instruction actually uses the PC (either RN == 15 indicates some other
> operation, or else it is specified as unpredictable).  So those should
> simply all be copied unmodified ...
> 

I can understand almost of your comments except this one.  I think you
are right, but there are still some cases that PC is used in this
category of instructions.

thumb2_copy_copro_load_store covers instructions STC/STC2, VLDR/VSTR and
LDC/LDC2 (literal and immediate).  I re-read ARM ARM again, and find that,

STC/STC2 doesn't use PC.  ARM ARM said "if n == 15 && (wback ||
CurrentInstrSet() != InstrSet_ARM) then UNPREDICTABLE;"

VSTR doesn't use PC.  ARM ARM said "if n == 15 && CurrentInstrSet() !=
InstrSet_ARM then UNPREDICTABLE;"

However, LDC/LDC2/VLDR can use PC.

VLDR<c><q>{.32} <Sd>, [PC, #+/-<imm>]

LDC, LDC2 (literal or immediate)
LDC{L}<c> <coproc>,<CRd>,[PC],<option>

I can write a real VLDR instruction using PC successfully.  Still no
luck to fix 'Illegal instruction' when running program having LDC/LDC2
using PC register, but I think LDC/LDC2 should be able to use PC
register.  Am I missing something here?

-- 
Yao (éå)


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]