Re: [PATCH] microMIPS support

["Maciej W. Rozycki" <macro at codesourcery dot com>]

On Thu, 17 May 2012, Eli Zaretskii wrote:

> >  I added only some of the menus by your explicit request.  You rejected my 
> > proposal that I made in response which added all of them and that was only 
> > trivially different to the version you have proposed now.
> 
> In that case, I apologize for my initial misunderstanding.

 Accepted, thank you.

> >  Certainly, next time I'll just drop any changes to the manual I disagree 
> > with.
> 
> I'd prefer that next time we could arrive at an agreement sooner.

 Me too, however I can't guarantee we'll always agree just as I couldn't 
agree with you on this occasion.  In which case I'd rather keep the 
functional bits and let you do with the corresponding manual updates 
whatever you want to, than drop everything.

> >  Thanks for your proposal, even though my original concern about pages 
> > containing single-entry menus still stands.  This doesn't really matter 
> > however for two reasons, first and foremost because you have the power to 
> > override my objection to any changes to the manual, and second because it 
> > contains changes irrelevant to my change and as such I cannot integrate 
> > them.  Please split changes to the existing pieces of the manual off and 
> > commit them separately.  I'll extract the rest and fold into my change.
> 
> Which changes are irrelevant?  I tried deliberately to put aside any
> such unrelated changes, but maybe I missed some.

 I have now extracted them and provided below, for a reference.  I have 
now committed them assuming that anything you have proposed has been 
self-approved.  I'll be providing the rest with the final version of the 
microMIPS change separately as soon as I have committed it straight away.

  Maciej

2011-05-18  Eli Zaretskii  <eliz@gnu.org>

	gdb/doc/
	* gdb.texinfo (Architecture-Specific Protocol Details): Define
	nodes for subsections.  Add @acronym mark-ups and adjust 
	formatting.

gdb-doc-acronym.diff
Index: gdb-fsf-trunk-quilt/gdb/doc/gdb.texinfo
===================================================================
--- gdb-fsf-trunk-quilt.orig/gdb/doc/gdb.texinfo	2012-05-18 23:22:56.135560932 +0100
+++ gdb-fsf-trunk-quilt/gdb/doc/gdb.texinfo	2012-05-18 23:24:04.235631195 +0100
@@ -36849,9 +36849,21 @@ This section describes how the remote pr
 target architectures.  Also see @ref{Standard Target Features}, for
 details of XML target descriptions for each architecture.
 
-@subsection ARM
+@menu
+* ARM-Specific Protocol Details::
+* MIPS-Specific Protocol Details::
+@end menu
 
-@subsubsection Breakpoint Kinds
+@node ARM-Specific Protocol Details
+@subsection @acronym{ARM}-specific Protocol Details
+
+@menu
+* ARM Breakpoint Kinds::
+@end menu
+
+@node ARM Breakpoint Kinds
+@subsubsection @acronym{ARM} Breakpoint Kinds
+@cindex breakpoint kinds, @acronym{ARM}
 
 These breakpoint kinds are defined for the @samp{Z0} and @samp{Z1} packets.
 
@@ -36864,31 +36876,35 @@ These breakpoint kinds are defined for t
 32-bit Thumb mode (Thumb-2) breakpoint.
 
 @item 4
-32-bit ARM mode breakpoint.
+32-bit @acronym{ARM} mode breakpoint.
 
 @end table
 
-@subsection MIPS
+@node MIPS-Specific Protocol Details
+@subsection @acronym{MIPS}-specific Protocol Details
 
-@subsubsection Register Packet Format
+@menu
+* MIPS Register packet Format::
+@end menu
+
+@node MIPS Register packet Format
+@subsubsection @acronym{MIPS} Register Packet Format
 
 The following @code{g}/@code{G} packets have previously been defined.
 In the below, some thirty-two bit registers are transferred as
 sixty-four bits.  Those registers should be zero/sign extended (which?)
 to fill the space allocated.  Register bytes are transferred in target
 byte order.  The two nibbles within a register byte are transferred
-most-significant - least-significant.
+most-significant -- least-significant.
 
 @table @r
 
 @item MIPS32
-
 All registers are transferred as thirty-two bit quantities in the order:
 32 general-purpose; sr; lo; hi; bad; cause; pc; 32 floating-point
 registers; fsr; fir; fp.
 
 @item MIPS64
-
 All registers are transferred as sixty-four bit quantities (including
 thirty-two bit registers such as @code{sr}).  The ordering is the same
 as @code{MIPS32}.