[PATCH 15/24] RISC-V sim: Improve cycle and instret counts.

[Mike Frysinger]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> @@ -2398,6 +2408,10 @@ initialize_cpu (SIM_DESC sd, SIM_CPU *cpu, int mhartid)
>  
>    cpu->csr.mimpid = 0x8000;
>    cpu->csr.mhartid = mhartid;
> +  cpu->csr.cycle = 0;
> +  cpu->csr.cycleh = 0;
> +  cpu->csr.instret = 0;
> +  cpu->csr.instreth = 0;

if this is done so we can re-initialize the CPU and have all the CSR's be
reset, we should do this with a single memset across all of cpu->csr right ?
are there any that should be preserved ?  if there were, i'd argue that cycle
falls into that bucket too.
-mike