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pending/1162: RE: Adding MAC registers on H8300 Simulator [H8S/2600]
- From: "D.Venkatasubramanian, Noida" <dvenkat at noida dot hcltech dot com>
- To: gdb-gnats at sources dot redhat dot com "'gdb-patches at sources dot redhat dot com'" <gdb-patches at sources dot redhat dot com>
- Cc: "D.Venkatasubramanian, Noida" <dvenkat at noida dot hcltech dot com>
- Date: Thu, 13 Mar 2003 15:22:45 +0530
- Subject: pending/1162: RE: Adding MAC registers on H8300 Simulator [H8S/2600]
>Number: 1162
>Category: pending
>Synopsis: RE: Adding MAC registers on H8300 Simulator [H8S/2600]
>Confidential: yes
>Severity: serious
>Priority: medium
>Responsible: unassigned
>State: open
>Class: change-request
>Submitter-Id: unknown
>Arrival-Date: Mon Mar 31 05:48:01 UTC 2003
>Closed-Date:
>Last-Modified:
>Originator:
>Release:
>Organization:
>Environment:
>Description:
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Hi,
OK, Here's the patch. It will flag an illegal
instruction when a "mac" instruction is
encountered. Otherwise, works fine for clrmac,
ldmac and stmac.
The MAC instruction requires a SYSR register,
but no description seems to be given about
that. Any ideas/suggestions on that front.
One more change required in binutils
(include/opcode/h8300.h) has already been
applied by Nick.
I succeeded in getting GDB to recognise the
mach and macl registers when the target is
H8S, but does not seem possible with the
current implementation to do so only for
H8S/2600. Will require an addition to the
target. Additional targets for H8 Series
was discussed on the Binutils list a while
ago, but nothing seems to have come out of
it.
Can you review the patch and give inputs.
Thanks and Regards,
Venky
---------------- sim/h8300 ---------------
2003-03-13 D.Venkatasubramanian <dvenkat at noida dot hcltech dot com>
* compile.c: Added #define OP_MACREG.
Added #define MACH_REGNUM and MACL_REGNUM.
(decode): Added MACREG support.
(fetch): Added OP_MACREG support.
(store): Added OP_MACREG support.
(sim_resume): Added support for O_CLRMAC,
O_LDMAC and O_STMAC.
* inst.h: Added n_mult, z_mult and v_mult variables
for N-MULT, Z-MULT and V-MULT flags.
Added mac_insn variable for setting a flag when a
MAC instruction is executed.
(struct cpu_state_type): Added mach and macl.
---------------- gdb/ -----------------------
2003-03-13 D.Venkatasubramanian <dvenkat at noida dot hcltech dot com>
* h8300-tdep.c: Incresed E_NUM_REGS by 2 for H8S.
(enum gdb_regnum): Added E_MACH_REGNUM, E_MACL_REGNUM.
(h8300_register_name): Added mach and macl for H8S.
(h8300_print_register): Print mach and macl values.
>-----Original Message-----
>From: D.Venkatasubramanian, Noida
>Sent: Thursday, March 13, 2003 11:13 AM
>To: Michael Snyder; 'gdb-patches at sources dot redhat dot com'
>Subject: RE: Adding MAC registers on H8300 Simulator [H8S/2600]
>
>
>
>>
>>"D.Venkatasubramanian, Noida" wrote:
>>>
>>> Hi All,
>>>
>>> As the H8S/2600 CPU has MAC registers, specifically
>>> MACH and MACL, I added them to the H8300 Simulator. How
>>> do I make GDB recognize these registers, more
>>> specifically, what are the files that need to be
>>> modified? In the simulator, I have added the registers
>>> in the cpu_state structure and some other places.
>>
>>Hi Venky --
>>
>>You did? I don't see your changes in the repository,
>>nor do I see your name in the ChangeLog.
>>
>>I would be interested in helping you get these changes in.
>>Can you send me your patches, or pointers to them?
>>
>
>Well, I did that locally, I will regenerate the patches
>and send it today. BTW, there was a problem, the
>description for the MAC instruction is not clear, it says,
>it requires a SYSR (System Register), but no such register
>seems to be described. I have disabled that instruction.
>Maybe, you could help me figure it out, how to go about it.
>
>>
>>> Also, how do I make these registers conditionally
>>> displayed on GDB when the CPU is H8S/2600.
>>
>>This sounds like a job for -- gdbarch!
>>Don't worry, it should not be too difficult.
>>
>>Michael
>>
>
>Venky
>
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2003-03-13 D.Venkatasubramanian <dvenkat at noida dot hcltech dot com>
* compile.c: Added #define OP_MACREG.
Added #define MACH_REGNUM and MACL_REGNUM.
(decode): Added MACREG support.
(fetch): Added OP_MACREG support.
(store): Added OP_MACREG support.
(sim_resume): Added support for O_CLRMAC,
O_LDMAC and O_STMAC.
* inst.h: Added n_mult, z_mult and v_mult variables
for N-MULT, Z-MULT and V-MULT flags.
Added mac_insn variable for setting a flag when a
MAC instruction is executed.
(struct cpu_state_type): Added mach and macl.
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Index: inst.h=0A=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A=
RCS file: /cvs/src/src/sim/h8300/inst.h,v=0A=
retrieving revision 1.4=0A=
diff -c -3 -p -r1.4 inst.h=0A=
*** inst.h 26 Dec 2002 05:44:46 -0000 1.4=0A=
--- inst.h 13 Mar 2003 09:22:48 -0000=0A=
*************** enum h8300_sim_state {=0A=
*** 66,71 ****=0A=
--- 66,77 ----=0A=
SIM_STATE_RUNNING, SIM_STATE_EXITED, SIM_STATE_SIGNALLED, =
SIM_STATE_STOPPED=0A=
};=0A=
=0A=
+ /* The N-MULT, Z-MULT and V-MULT Flags defined in H8S/2600 =
Architectures. */=0A=
+ int n_mult, z_mult, v_mult;=0A=
+ =0A=
+ /* Was a MAC instruction executed? */=0A=
+ int mac_insn;=0A=
+ =0A=
typedef struct=0A=
{=0A=
enum h8300_sim_state state;=0A=
*************** typedef struct=0A=
*** 88,93 ****=0A=
--- 94,103 ----=0A=
int insts;=0A=
int ticks;=0A=
int compiles;=0A=
+ /* H8S only. */=0A=
+ unsigned int macl;=0A=
+ unsigned int mach;=0A=
+ /* --- */=0A=
#ifdef ADEBUG=0A=
int stats[O_LAST];=0A=
#endif=0A=
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name="h8300-tdep_patch.txt"
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filename="h8300-tdep_patch.txt"
Index: h8300-tdep.c=0A=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A=
RCS file: /cvs/src/src/gdb/h8300-tdep.c,v=0A=
retrieving revision 1.41=0A=
diff -c -3 -p -r1.41 h8300-tdep.c=0A=
*** h8300-tdep.c 12 Mar 2003 16:50:44 -0000 1.41=0A=
--- h8300-tdep.c 13 Mar 2003 09:27:44 -0000=0A=
*************** struct frame_extra_info=0A=
*** 44,50 ****=0A=
CORE_ADDR locals_pointer;=0A=
};=0A=
=0A=
! #define E_NUM_REGS (h8300smode ? 14 : 13)=0A=
=0A=
enum=0A=
{=0A=
--- 44,52 ----=0A=
CORE_ADDR locals_pointer;=0A=
};=0A=
=0A=
! /* H8S has MAC registers. */=0A=
! #define E_NUM_REGS (h8300smode ? 16 : 13)=0A=
! =0A=
=0A=
enum=0A=
{=0A=
*************** enum gdb_regnum=0A=
*** 69,75 ****=0A=
E_CYCLES_REGNUM,=0A=
E_TICK_REGNUM, E_EXR_REGNUM =3D E_TICK_REGNUM,=0A=
E_INST_REGNUM, E_TICKS_REGNUM =3D E_INST_REGNUM,=0A=
! E_INSTS_REGNUM=0A=
};=0A=
=0A=
#define UNSIGNED_SHORT(X) ((X) & 0xffff)=0A=
--- 71,79 ----=0A=
E_CYCLES_REGNUM,=0A=
E_TICK_REGNUM, E_EXR_REGNUM =3D E_TICK_REGNUM,=0A=
E_INST_REGNUM, E_TICKS_REGNUM =3D E_INST_REGNUM,=0A=
! E_INSTS_REGNUM,=0A=
! E_MACH_REGNUM,=0A=
! E_MACL_REGNUM=0A=
};=0A=
=0A=
#define UNSIGNED_SHORT(X) ((X) & 0xffff)=0A=
*************** h8300_register_name (int regno)=0A=
*** 860,870 ****=0A=
type is selected. */=0A=
static char *h8300_register_names[] =3D {=0A=
"r0", "r1", "r2", "r3", "r4", "r5", "r6",=0A=
! "sp", "ccr","pc","cycles", "tick", "inst", ""=0A=
};=0A=
static char *h8300s_register_names[] =3D {=0A=
"er0", "er1", "er2", "er3", "er4", "er5", "er6",=0A=
! "sp", "ccr", "pc", "cycles", "exr", "tick", "inst"=0A=
};=0A=
char **register_names =3D=0A=
h8300smode ? h8300s_register_names : h8300_register_names;=0A=
--- 864,878 ----=0A=
type is selected. */=0A=
static char *h8300_register_names[] =3D {=0A=
"r0", "r1", "r2", "r3", "r4", "r5", "r6",=0A=
! "sp", "ccr","pc","cycles", "tick", "inst", "",=0A=
! "", ""=0A=
};=0A=
+ =0A=
+ /* Adding mach and macl registers. */=0A=
static char *h8300s_register_names[] =3D {=0A=
"er0", "er1", "er2", "er3", "er4", "er5", "er6",=0A=
! "sp", "ccr", "pc", "cycles", "exr", "tick", "inst", =0A=
! "mach", "macl"=0A=
};=0A=
char **register_names =3D=0A=
h8300smode ? h8300s_register_names : h8300_register_names;=0A=
*************** h8300_print_register (struct gdbarch *gd=0A=
*** 963,968 ****=0A=
--- 971,981 ----=0A=
fprintf_filtered (file, "I2-%d ", (l & 4) !=3D 0);=0A=
fprintf_filtered (file, "I1-%d ", (l & 2) !=3D 0);=0A=
fprintf_filtered (file, "I0-%d", (l & 1) !=3D 0);=0A=
+ }=0A=
+ else if ((regno =3D=3D E_MACH_REGNUM && h8300smode) =0A=
+ || (regno =3D=3D E_MACL_REGNUM && h8300smode))=0A=
+ {=0A=
+ fprintf_filtered (file, "0x%04lx %-4ld", val, val);=0A=
}=0A=
fprintf_filtered (file, "\n");=0A=
}=0A=
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filename="gdb_ChangeLog.txt"
2003-03-13 D.Venkatasubramanian <dvenkat at noida dot hcltech dot com>
* h8300-tdep.c: Incresed E_NUM_REGS by 2 for H8S.
(enum gdb_regnum): Added E_MACH_REGNUM, E_MACL_REGNUM.
(h8300_register_name): Added mach and macl for H8S.
(h8300_print_register): Print mach and macl values.
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Content-Type: text/plain;
name="compile_patch.txt"
Content-Transfer-Encoding: quoted-printable
Content-Disposition: attachment;
filename="compile_patch.txt"
Index: compile.c=0A=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0A=
RCS file: /cvs/src/src/sim/h8300/compile.c,v=0A=
retrieving revision 1.23=0A=
diff -c -3 -p -r1.23 compile.c=0A=
*** compile.c 27 Feb 2003 23:26:33 -0000 1.23=0A=
--- compile.c 13 Mar 2003 09:20:41 -0000=0A=
*************** void sim_set_simcache_size PARAMS ((int)=0A=
*** 69,74 ****=0A=
--- 69,77 ----=0A=
#define OP_IMM 8=0A=
#define OP_ABS 10=0A=
#define OP_EXR 11=0A=
+ /* MAC register in H8S only. */=0A=
+ #define OP_MACREG 12=0A=
+ =0A=
#define h8_opcodes ops=0A=
#define DEFINE_TABLE=0A=
#include "opcode/h8300.h"=0A=
*************** decode (int addr, unsigned char *data, d=0A=
*** 333,338 ****=0A=
--- 336,346 ----=0A=
=0A=
bit =3D thisnib;=0A=
}=0A=
+ /* For MAC related instructions. */=0A=
+ else if (looking_for & MACREG)=0A=
+ {=0A=
+ abs =3D (thisnib =3D=3D 3);=0A=
+ }=0A=
else if (looking_for =3D=3D E)=0A=
{=0A=
dst->op =3D q;=0A=
*************** decode (int addr, unsigned char *data, d=0A=
*** 372,377 ****=0A=
--- 380,392 ----=0A=
p->type =3D X (OP_REG, size);=0A=
p->reg =3D rn;=0A=
}=0A=
+ /* For MAC related instructions. */=0A=
+ else if (x & MACREG)=0A=
+ {=0A=
+ size =3D bitfrom (x);=0A=
+ p->type =3D X (OP_MACREG, size);=0A=
+ p->reg =3D abs ? 1 : 0;=0A=
+ }=0A=
else if (x & INC)=0A=
{=0A=
p->type =3D X (OP_INC, size);=0A=
*************** fetch (ea_type *arg)=0A=
*** 562,567 ****=0A=
--- 577,587 ----=0A=
return GET_W_REG (rn);=0A=
case X (OP_REG, SL):=0A=
return GET_L_REG (rn);=0A=
+ =0A=
+ /* MAC registers in H8S only. */=0A=
+ case X (OP_MACREG, SL):=0A=
+ return GET_L_REG (rn);=0A=
+ =0A=
case X (OP_IMM, SB):=0A=
case X (OP_IMM, SW):=0A=
case X (OP_IMM, SL):=0A=
*************** store (ea_type *arg, int n)=0A=
*** 646,651 ****=0A=
--- 666,676 ----=0A=
case X (OP_REG, SL):=0A=
SET_L_REG (rn, n);=0A=
break;=0A=
+ =0A=
+ /* MAC registers in H8S only. */=0A=
+ case X (OP_MACREG, SL):=0A=
+ SET_L_REG (rn, n);=0A=
+ break;=0A=
=0A=
case X (OP_DEC, SB):=0A=
t =3D GET_L_REG (rn) - 1;=0A=
*************** sim_stop (SIM_DESC sd)=0A=
*** 955,960 ****=0A=
--- 980,989 ----=0A=
#define EXR_REGNUM 11=0A=
#define INST_REGNUM 12=0A=
#define TICK_REGNUM 13=0A=
+ /* Only on the H8S Series. */=0A=
+ #define MACH_REGNUM 14=0A=
+ #define MACL_REGNUM 15=0A=
+ =0A=
=0A=
void=0A=
sim_resume (SIM_DESC sd, int step, int siggnal)=0A=
*************** sim_resume (SIM_DESC sd, int step, int s=0A=
*** 1385,1390 ****=0A=
--- 1414,1487 ----=0A=
if ((V =3D=3D 1))=0A=
goto condtrue;=0A=
goto next;=0A=
+ =0A=
+ /* MAC related instructions. */=0A=
+ case O (O_CLRMAC, SN):=0A=
+ {=0A=
+ if (h8300smode)=0A=
+ {=0A=
+ cpu.mach =3D 0x0;=0A=
+ cpu.macl =3D 0x0;=0A=
+ mac_insn =3D 0;=0A=
+ }=0A=
+ else=0A=
+ goto illegal;=0A=
+ }=0A=
+ goto next;=0A=
+ case O (O_LDMAC, SL):=0A=
+ {=0A=
+ if (h8300smode)=0A=
+ {=0A=
+ res =3D GET_L_REG (code->src.reg);=0A=
+ if (code->dst.reg =3D=3D 1)=0A=
+ {=0A=
+ cpu.macl =3D res;=0A=
+ }=0A=
+ else=0A=
+ {=0A=
+ cpu.mach |=3D 0x3FF;=0A=
+ res &=3D 0x3FF;=0A=
+ cpu.mach &=3D res;=0A=
+ }=0A=
+ mac_insn =3D 0;=0A=
+ }=0A=
+ else=0A=
+ goto illegal;=0A=
+ }=0A=
+ goto next;=0A=
+ case O (O_STMAC, SL):=0A=
+ {=0A=
+ if (h8300smode)=0A=
+ {=0A=
+ if (code->src.reg =3D=3D 1)=0A=
+ {=0A=
+ res =3D cpu.macl;=0A=
+ }=0A=
+ else=0A=
+ {=0A=
+ int extend =3D 0;=0A=
+ res =3D cpu.mach;=0A=
+ cpu.mach &=3D 0x0;=0A=
+ res &=3D 0x3FF;=0A=
+ extend =3D res & 0x200;=0A=
+ if (extend !=3D 0)=0A=
+ {=0A=
+ res |=3D 0xFFFFFC00;=0A=
+ }=0A=
+ }=0A=
+ SET_L_REG (code->dst.reg, res);=0A=
+ goto just_flags_stmac;=0A=
+ }=0A=
+ else=0A=
+ goto illegal;=0A=
+ }=0A=
+ goto next;=0A=
+ =0A=
+ case O (O_MAC, SL):=0A=
+ {=0A=
+ goto illegal;=0A=
+ }=0A=
+ goto next;=0A=
=0A=
case O (O_SYSCALL, SB):=0A=
{=0A=
*************** sim_resume (SIM_DESC sd, int step, int s=0A=
*** 1842,1847 ****=0A=
--- 1939,1957 ----=0A=
}=0A=
goto next;=0A=
=0A=
+ just_flags_stmac:=0A=
+ if (mac_insn =3D=3D 0)=0A=
+ {=0A=
+ v =3D 0;=0A=
+ }=0A=
+ else=0A=
+ {=0A=
+ n =3D n_mult;=0A=
+ nz =3D z_mult;=0A=
+ v =3D v_mult;=0A=
+ }=0A=
+ goto next;=0A=
+ =0A=
next:;=0A=
pc =3D code->next_pc;=0A=
=0A=
*************** sim_store_register (SIM_DESC sd, int rn,=0A=
*** 1960,1965 ****=0A=
--- 2070,2085 ----=0A=
case TICK_REGNUM:=0A=
cpu.ticks =3D longval;=0A=
break;=0A=
+ =0A=
+ /* Only for the H8S Series. */=0A=
+ case MACL_REGNUM:=0A=
+ cpu.macl =3D intval;=0A=
+ break;=0A=
+ =0A=
+ case MACH_REGNUM:=0A=
+ cpu.mach =3D intval;=0A=
+ break;=0A=
+ =0A=
}=0A=
return -1;=0A=
}=0A=
*************** sim_fetch_register (SIM_DESC sd, int rn,=0A=
*** 2009,2014 ****=0A=
--- 2129,2144 ----=0A=
v =3D cpu.insts;=0A=
longreg =3D 1;=0A=
break;=0A=
+ =0A=
+ /* Only for the H8S Series. */=0A=
+ case MACL_REGNUM:=0A=
+ v =3D cpu.macl;=0A=
+ break;=0A=
+ =0A=
+ case MACH_REGNUM:=0A=
+ v =3D cpu.mach;=0A=
+ break;=0A=
+ =0A=
}=0A=
if (h8300hmode || longreg)=0A=
{=0A=
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>How-To-Repeat:
>Fix:
>Release-Note:
>Audit-Trail:
>Unformatted: