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sim/1290: Some fixes for SH gencode.c - mainly autoincrement
- From: dmcq2002 at yahoo dot co dot uk
- To: gdb-gnats at sources dot redhat dot com
- Date: 18 Jul 2003 17:21:27 -0000
- Subject: sim/1290: Some fixes for SH gencode.c - mainly autoincrement
- Reply-to: dmcq2002 at yahoo dot co dot uk
>Number: 1290
>Category: sim
>Synopsis: Some fixes for SH gencode.c - mainly autoincrement
>Confidential: no
>Severity: serious
>Priority: medium
>Responsible: unassigned
>State: open
>Class: change-request
>Submitter-Id: net
>Arrival-Date: Fri Jul 18 17:28:00 UTC 2003
>Closed-Date:
>Last-Modified:
>Originator: dmcq2002@yahoo.co.uk
>Release: GDB 5.3
>Organization:
>Environment:
I don't have a environment to run gdb in so the release number is just to say I've compared with the latest source.
>Description:
I've attached a diff -pcw with the latest source I can find in sim/sh/gencode.c 1.8 showing various fixes.
They are to fix:
Autoincrement and autodecrement when the address register is the same as the register being loaded or stored.
A problem with the stable sort, the method there at the moment may not work sometimes. I've put in an original order number to sort against. (Perhaps the linux qsort does something to avoid this problem?)
A problem with transferring between FPUL and a floating point register. It should not use floats at all whilst doing this as the host may change NaNs on the fly from signalling to quiet NaNs - and the operations may act on the lower half of doubles which look like NaNs.
A comment end marker missing from a generated line thus chopping out some code.
>How-To-Repeat:
I haven't got a linux system to run things on so I haven't been able to test actually compiling with gdb - I've just been hacking the simulator itself.
The one that mightn't be obvious is the floating point one, and qsort may be stable on linux. I'm not sure what you're sh assembler is like but this is the equivalent of loading a double using two integer registers - and the double gets the wrong value:
the double may end up as
0x41e00000ffe00000
whereas it should be
0x3ff00000ffa00000
mov.l =0x3ff00000, r2
mov.l =0xffa00000, r4
mov.l =0x00280800, r0
lds r0, fpscr
lds r4, fpul
fsts fpul, fr9 ; can go wrong
lds r2, fpul
fsts fpul, fr8
>Fix:
Proposed patches in attached diff.txt. gencode.c is the original sim/sh/gencode.c 1.8 and gencode2.c is it with fixes.
>Release-Note:
>Audit-Trail:
>Unformatted:
----gnatsweb-attachment----
Content-Type: text/plain; name="diff.txt"
Content-Disposition: inline; filename="diff.txt"
*** gencode.c Fri Jul 18 16:32:28 2003
--- gencode2.c Fri Jul 18 17:28:41 2003
*************** typedef struct
*** 41,46 ****
--- 41,47 ----
char *code;
char *stuff[MAX_NR_STUFF];
int index;
+ int order;
} op;
*************** op tab[] =
*** 305,317 ****
/* sh2e */
{ "", "", "flds <FREG_N>,FPUL", "1111nnnn00011101",
! " union",
! " {",
! " int i;",
! " float f;",
! " } u;",
! " u.f = FR(n);",
! " FPUL = u.i;",
},
/* sh2e */
--- 306,312 ----
/* sh2e */
{ "", "", "flds <FREG_N>,FPUL", "1111nnnn00011101",
! " FPUL = FI(n);",
},
/* sh2e */
*************** op tab[] =
*** 342,348 ****
"}",
"else",
"{",
! " SET_FR (n, FR (m));",
"}",
},
/* sh2e */
--- 337,343 ----
"}",
"else",
"{",
! " SET_FI (n, FI (m));",
"}",
},
/* sh2e */
*************** op tab[] =
*** 478,490 ****
/* sh2e */
{ "", "", "fsts FPUL,<FREG_N>", "1111nnnn00001101",
! " union",
! " {",
! " int i;",
! " float f;",
! " } u;",
! " u.i = FPUL;",
! " SET_FR (n, u.f);",
},
{ "", "n", "jmp @<REG_N>", "0100nnnn00101011",
--- 473,479 ----
/* sh2e */
{ "", "", "fsts FPUL,<FREG_N>", "1111nnnn00001101",
! " SET_FI (n, FPUL);",
},
{ "", "n", "jmp @<REG_N>", "0100nnnn00101011",
*************** op tab[] =
*** 582,588 ****
},
{ "", "nm", "mac.w @<REG_M>+,@<REG_N>+", "0100nnnnmmmm1111",
! "macw(R0,memory,n,m,endianw);",
},
{ "n", "", "mov #<imm>,<REG_N>", "1110nnnni8*1....",
--- 571,577 ----
},
{ "", "nm", "mac.w @<REG_M>+,@<REG_N>+", "0100nnnnmmmm1111",
! "macw(R,memory,n,m,endianw);",
},
{ "n", "", "mov #<imm>,<REG_N>", "1110nnnni8*1....",
*************** op tab[] =
*** 610,616 ****
{ "n", "m", "mov.b @<REG_M>+,<REG_N>", "0110nnnnmmmm0100",
"MA (1);",
"R[n] = RSBAT (R[m]);",
! "R[m] += 1;",
"L (n);",
},
{ "", "mn", "mov.b <REG_M>,@<REG_N>", "0010nnnnmmmm0000",
--- 599,605 ----
{ "n", "m", "mov.b @<REG_M>+,<REG_N>", "0110nnnnmmmm0100",
"MA (1);",
"R[n] = RSBAT (R[m]);",
! "if (n != m) R[m] += 1;",
"L (n);",
},
{ "", "mn", "mov.b <REG_M>,@<REG_N>", "0010nnnnmmmm0000",
*************** op tab[] =
*** 631,638 ****
},
{ "", "nm", "mov.b <REG_M>,@-<REG_N>", "0010nnnnmmmm0100",
"MA (1);",
"R[n] -= 1;",
- "WBAT (R[n], R[m]);",
},
{ "n", "m", "mov.b @<REG_M>,<REG_N>", "0110nnnnmmmm0000",
"MA (1);",
--- 620,627 ----
},
{ "", "nm", "mov.b <REG_M>,@-<REG_N>", "0010nnnnmmmm0100",
"MA (1);",
+ "WBAT (R[n] - 1, R[m]);",
"R[n] -= 1;",
},
{ "n", "m", "mov.b @<REG_M>,<REG_N>", "0110nnnnmmmm0000",
"MA (1);",
*************** op tab[] =
*** 663,669 ****
{ "nm", "m", "mov.l @<REG_M>+,<REG_N>", "0110nnnnmmmm0110",
"MA (1);",
"R[n] = RLAT (R[m]);",
! "R[m] += 4;",
"L (n);",
},
{ "n", "m", "mov.l @<REG_M>,<REG_N>", "0110nnnnmmmm0010",
--- 652,658 ----
{ "nm", "m", "mov.l @<REG_M>+,<REG_N>", "0110nnnnmmmm0110",
"MA (1);",
"R[n] = RLAT (R[m]);",
! "if (n != m) R[m] += 4;",
"L (n);",
},
{ "n", "m", "mov.l @<REG_M>,<REG_N>", "0110nnnnmmmm0010",
*************** op tab[] =
*** 685,692 ****
},
{ "", "nm", "mov.l <REG_M>,@-<REG_N>", "0010nnnnmmmm0110",
"MA (1) ;",
"R[n] -= 4;",
- "WLAT (R[n], R[m]);",
},
{ "", "nm", "mov.l <REG_M>,@<REG_N>", "0010nnnnmmmm0010",
"MA (1);",
--- 674,681 ----
},
{ "", "nm", "mov.l <REG_M>,@-<REG_N>", "0010nnnnmmmm0110",
"MA (1) ;",
+ "WLAT (R[n] - 4, R[m]);",
"R[n] -= 4;",
},
{ "", "nm", "mov.l <REG_M>,@<REG_N>", "0010nnnnmmmm0010",
"MA (1);",
*************** op tab[] =
*** 716,722 ****
{ "nm", "n", "mov.w @<REG_M>+,<REG_N>", "0110nnnnmmmm0101",
"MA (1);",
"R[n] = RSWAT (R[m]);",
! "R[m] += 2;",
"L (n);",
},
{ "n", "m", "mov.w @<REG_M>,<REG_N>", "0110nnnnmmmm0001",
--- 705,711 ----
{ "nm", "n", "mov.w @<REG_M>+,<REG_N>", "0110nnnnmmmm0101",
"MA (1);",
"R[n] = RSWAT (R[m]);",
! "if (n != m) R[m] += 2;",
"L (n);",
},
{ "n", "m", "mov.w @<REG_M>,<REG_N>", "0110nnnnmmmm0001",
*************** op tab[] =
*** 738,745 ****
},
{ "n", "mn", "mov.w <REG_M>,@-<REG_N>", "0010nnnnmmmm0101",
"MA (1);",
"R[n] -= 2;",
- "WWAT (R[n], R[m]);",
},
{ "", "nm", "mov.w <REG_M>,@<REG_N>", "0010nnnnmmmm0001",
"MA (1);",
--- 727,734 ----
},
{ "n", "mn", "mov.w <REG_M>,@-<REG_N>", "0010nnnnmmmm0101",
"MA (1);",
+ "WWAT (R[n] - 2, R[m]);",
"R[n] -= 2;",
},
{ "", "nm", "mov.w <REG_M>,@<REG_N>", "0010nnnnmmmm0001",
"MA (1);",
*************** qfunc (a, b)
*** 1898,1904 ****
diff = strcmp (bufa, bufb);
/* Stabilize the sort, so that later entries can override more general
preceding entries. */
! return diff ? diff : a - b;
}
static void
--- 1887,1893 ----
diff = strcmp (bufa, bufb);
/* Stabilize the sort, so that later entries can override more general
preceding entries. */
! return diff ? diff : a->order - b->order;
}
static void
*************** sorttab ()
*** 1906,1914 ****
--- 1895,1905 ----
{
op *p = tab;
int len = 0;
+ int order = 0; /* for stable sort */
while (p->name)
{
+ p->order = order++;
p++;
len++;
}
*************** ppi_gensim ()
*** 2523,2529 ****
printf (" DSR |= res_grd >> 7 & 1;\n");
printf (" case 2: /* Zero Value Mode */\n");
printf (" DSR |= DSR >> 6 & 1;\n");
! printf (" case 3: /* Overflow mode\n");
printf (" DSR |= overflow >> 4;\n");
printf (" case 4: /* Signed Greater Than Mode */\n");
printf (" DSR |= DSR >> 7 & 1;\n");
--- 2514,2520 ----
printf (" DSR |= res_grd >> 7 & 1;\n");
printf (" case 2: /* Zero Value Mode */\n");
printf (" DSR |= DSR >> 6 & 1;\n");
! printf (" case 3: /* Overflow mode */\n");
printf (" DSR |= overflow >> 4;\n");
printf (" case 4: /* Signed Greater Than Mode */\n");
printf (" DSR |= DSR >> 7 & 1;\n");