Re: Data on 3DNow?

[Jeff Epler <jepler at inetnebr dot com>]

On Tue, Oct 12, 1999 at 05:41:39PM -0500, Jim Blandy wrote:
> 
> Can anyone point me at web documentation for the 3DNow extensions to
> the IA32?

AMD has instruction set docs at
	http://www.amd.com/K6/k6docs/index.html
including
	http://www.amd.com/K6/k6docs/pdf/21928.pdf
docs on athlon (a few more instructions) are available nearby.

gas has support for as and objdump to assemble and disassemble 3DNow!
instructions (all those documented for the K6-2, not the two undocumented
opcodes, nor the new K7 opcodes), but at the time the work was done the
libbfds in binutils and in gdb were too different for the same patch to
work unchanged on both.  The short story is that all 3DNow! opcodes begin
"0f 0f", then the mod/rm byte (I think that's the right term), any other
operand bytes (sib, displacement), and then a single byte specifying
the actual operation.  Thus,
	0f 0f c0 b4
means "pfmul %mm0, %mm0", since b4 is the opcode for pfmul.  (All the
opcodes are of the form reg1 := reg1 OP mem_or_reg2)

Besides disassembly, the important thing to support for 3dnow! is to show
the FP registers as containing two 'float'-types.  For instance, running
the following code:
	int f=1.0, g=2.5;
	main() {
		__asm__("movq f, %mm0");
		*(char*)0=0;
	}
"info all-registers" will show:
     st0: 0xffff402000003f800000  Valid Unsupp                    NaN
but one would wish to see
     mm0: 0xffff402000003f800000  1.00000e00|2.500000e00
or the like.

Jeff
-- 
\/ http://www.freshmeat.net/                     Jeff Epler jepler@inetnebr.com
A Law of Computer Programming:
	Make it possible for programmers to write in English
	and you will find that programmers cannot write in English.