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Spec; Was: tracepoints implementation: bug in byte code generating.
- To: jtc at redback dot com
- Subject: Spec; Was: tracepoints implementation: bug in byte code generating.
- From: Andrew Cagney <ac131313 at cygnus dot com>
- Date: Wed, 15 Nov 2000 00:57:32 +1100
- Cc: gdb at sources dot redhat dot com
- References: <00c801c02c9a$fe671c90$6c219fa8@lss.emc.com> <39D8D1CE.3059@redhat.com> <004e01c039d8$774c1d50$6c219fa8@lss.emc.com> <39EF3020.3F6A@redhat.com> <005b01c039f6$f46b1390$6c219fa8@lss.emc.com> <39EF381C.7EE6@redhat.com> <006101c039f9$df09df60$6c219fa8@lss.emc.com> <5mvguo5spm.fsf@jtc.redback.com> <008501c03aad$46c9d700$6c219fa8@lss.emc.com> <5m66mncnpc.fsf@jtc.redback.com>
"J.T. Conklin" wrote:
> 4. COMMANDS
>
> 4.1 REGISTER FETCH
>
> input:
> context_t id;
> int offset; offset within register data
> int length; length of transfer
>
> output:
> int status;
> char data[];
>
> This command may yeild unpredicable results if context <id> has not
> been suspended.
>
> issues:
> This assumes a single flat address space for all registers.
> It might be convienent to have separate (but potentially
> overlapping) register files for integer registers, floating
> point registers, system registers, miscellaneous registers,
> etc.
>
> For example, one register file could contain the PC, FP, SP,
> and whatever other registers are needed on a particular
> architecture for GDB after a signal/exception/breakpoint
> event. This would solve the problem of what to return in
> those events.
One problem with this on targets that like to switch their byte order
(yes not very many :-).
The register data is, by definition, target byte order dependant.
Consequently, when GDB connects to the target it needs to know that
targets byte order for it to correctly interpret register values.
I suspect something that defines the register values in a byte-order
independant way may be better. Something based more on the P packet
(but network byte ordered).
Andrew