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Re: MIPS o32 ABI spec, $fp1 valid?
- From: David Anderson <davea at quasar dot engr dot sgi dot com>
- To: cgd at broadcom dot com, ac131313 at redhat dot com
- Cc: gdb at sources dot redhat dot com, drow at mvista dot com
- Date: Tue, 17 Jun 2003 13:12:39 -0700 (PDT)
- Subject: Re: MIPS o32 ABI spec, $fp1 valid?
Andrew Cagney <ac131313@redhat.com> writes:
>Does the o32 ABI specify how to spill a loating point register (a spill
>is different to a double store of a parameter as a spilt register is
>recovered by the unwind code. mdebug might, for instance, specify
>something.
No, mdebug says nothing about how spills are done (it says nothing
about how exactly float/double are stored, AFAICT).
The hardware requires mentioning the odd regs to get the entire
64 bits stored. In MIPS1.
Here is some mips1 o32 disassembly output, IRIX, so big-endian:
Given
...stuff
double x1(double d)
{
double d2 = d + 3.0;
d2 += x2(5.0);
return d2/4.5;
}
...stuff
x1:
[ 11] 0x 48: 3c 1c 00 00 lui $gp,0
[ 11] 0x 4c: 27 9c 00 00 addiu $gp,$gp,0
[ 11] 0x 50: 03 99 e0 21 addu $gp,$gp,$25
[ 11] 0x 54: 27 bd ff c8 addiu $sp,$sp,-56
[ 11] 0x 58: e7 ad 00 38 swc1 $f13,56($sp)
[ 11] 0x 5c: e7 ac 00 3c swc1 $f12,60($sp)
[ 12] 0x 60: 3c 01 40 08 lui $1,16392
[ 12] 0x 64: 44 81 38 00 mtc1 $1,$f7
[ 12] 0x 68: c7 a4 00 3c lwc1 $f4,60($sp)
[ 12] 0x 6c: c7 a5 00 38 lwc1 $f5,56($sp)
[ 12] 0x 70: 44 80 30 00 mtc1 $0,$f6
[ 13] 0x 74: 8f 99 00 00 lw $25,0($gp)
[ 12] 0x 78: 46 26 22 00 add.d $f8,$f4,$f6
[ 13] 0x 7c: 3c 01 40 14 lui $1,16404
[ 11] 0x 80: af bf 00 24 sw $31,36($sp)
[ 13] 0x 84: 44 81 68 00 mtc1 $1,$f13
[ 13] 0x 88: 44 80 60 00 mtc1 $0,$f12
[ 11] 0x 8c: af bc 00 20 sw $gp,32($sp)
[ 11] 0x 90: e7 b5 00 18 swc1 $f21,24($sp)
[ 11] 0x 94: e7 b4 00 1c swc1 $f20,28($sp)
[ 12] 0x 98: e7 a8 00 34 swc1 $f8,52($sp)
[ 13] 0x 9c: 03 20 f8 09 jalr $25
[ 12] 0x a0: e7 a9 00 30 swc1 $f9,48($sp)
[ 13] 0x a4: c7 ab 00 30 lwc1 $f11,48($sp)
[ 13] 0x a8: c7 aa 00 34 lwc1 $f10,52($sp)
[ 13] 0x ac: 46 20 05 06 mov.d $f20,$f0
[ 13] 0x b0: 46 34 54 00 add.d $f16,$f10,$f20
[ 14] 0x b4: 3c 01 40 12 lui $1,16402
[ 14] 0x b8: 44 81 98 00 mtc1 $1,$f19
[ 14] 0x bc: 44 80 90 00 mtc1 $0,$f18
[ 14] 0x c0: 8f bf 00 24 lw $31,36($sp)
[ 13] 0x c4: e7 b0 00 34 swc1 $f16,52($sp)
[ 13] 0x c8: e7 b1 00 30 swc1 $f17,48($sp)
[ 13] 0x cc: 8f bc 00 20 lw $gp,32($sp)
[ 14] 0x d0: c7 b4 00 1c lwc1 $f20,28($sp)
[ 14] 0x d4: c7 b5 00 18 lwc1 $f21,24($sp)
[ 14] 0x d8: 27 bd 00 38 addiu $sp,$sp,56
[ 14] 0x dc: 03 e0 00 08 jr $31
[ 14] 0x e0: 46 32 80 03 div.d $f0,$f16,$f18
Looking at cc -S output we see the fp regs are not invidually
mentioned:
# 9 }
# 10 double x1(double d)
# 11 {
.ent x1 2
x1:
.option O1
.set noreorder
.cpload $25
.set reorder
subu $sp, 56
sw $31, 36($sp)
.cprestore 32
s.d $f12, 56($sp)
s.d $f20, 24($sp)
.mask 0x90000000, -20
.fmask 0x00300000, -32
.frame $sp, 56, $31
.loc 2 11
...
Now I must admit I am using a modern compiler, not an original
old mips1 compiler. So while the spill would be the same,
(and same as reg saves) I don't recall precisely how it would
really look in IRIX mips1 assembler.
Regards,
David B. Anderson davea@sgi.com http://reality.sgiweb.org/davea