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Re: [avr] gas support for cfi info


On 16 February 2011 23:28, Richard Henderson <rth@redhat.com> wrote:
> On 02/15/2011 02:44 PM, Petr Hluzín wrote:
>> In avr-tdep.c [1] near avr_dwarf_reg_to_regnum():
>> /* Unfortunately dwarf2 register for SP is 32. ?*/
>
> Excellent. ?We're all on the same page for this.
>
>> (I can't help you with the value for #define DWARF2_DEFAULT_RETURN_COLUMN ?36)
>> AFAIK there is no written ABI. Only the calling convention is
>> documented (and only the easy cases), the rest is in gdb/gcc/binutils
>> sources and people's heads.
>
> As I recall, GCC defaults to using FIRST_PSEUDO_REGISTER for this,
> so as to not overlap any hard registers. ?I'll continue to so the same.
>
>> ? /* Avr-6 call instructions save 3 bytes. ?*/
>> ? switch (info.bfd_arch_info->mach)
>
> Thanks. ?That value is readily available in the assembler as well.
>
> Anitha pointed out to me via gcc pr17994 that AVR uses post-decrement
> for its pushes. ?I had a brief read over the AVR insn manual, and it's
> not crystal clear how multi-byte post-decrement pushes operate.
>
> I've made an assumption that it happens as-if each byte is pushed
> separately. ?I.e.
>
> ?caller: ? ? ? ? ? callee:
> ? ?save rN
> ? ?save rM
> ? ?trash ? ?<- SP ?hi(ret) ?<- CFA
> ? ? ? ? ? ? ? ? ? ?lo(ret)
> ? ? ? ? ? ? ? ? ? ?trash ? ?<- SP
>
> This is the only way I can imagine that call insns interoperate with
> byte push/pop insns.
>

The stack layout is correct. For call/rcall instructions, PC-low is
pushed first followed by a PC-high. (I just verified by
running/debugging a small app on the device)

> All of which means that the return address is at a different offset
> from the CFA than I originally thought. ?This ought to be fixed in
> the following.


Can you please explain the logic behind the following lines in gcc patch:


-         offset = -cfa_store.offset;
+         if (GET_CODE (XEXP (dest, 0)) == POST_DEC)
+           offset += -cfa_store.offset;
+         else
+           offset = -cfa_store.offset;



>
> Can someone please test these two patches and see if they actually
> agree with the hardware?

I have tried only compiler patch. Please refer to the attached output
for a small testcase. (avr-objdump -WfF). It appeared correct to me.

However I have one simple question with regarding the output: The CFI
instructions for registers have changed only after the prologue. (For
convenience I have attached disassembly too). As far as I understand,
DWARF2 spec emits CFI instructions immediately. (Appendix 5 of DWARF2
specification)

The other scenario is - how about functions with signals/interrupts?
The compiler will give an ICE compiling a function as below:

void my_interrupt_handler() __attribute__ (("interrupt"));

Likewise, for signal attribute too. I am going to apply assembler
patch and test it. Will get back on it shortly.

Anitha

>
> r~
>

Attachment: call-saved.txt
Description: Text document

int foo() {

	register a1, b1, c1, d1, e1, f1, g1, h1;
	register a2, b2, c2, d2, e2, f2, g2, h2;

	register result1 = a1+b1+c1+d1+e1+f1+g1+h1;
	register result2 = a2+b2+c2+d2+e2+f2+g2+h2;

	
	register result = result1 + result2;

	return result;
}

void main() {
	return foo();

}

Attachment: call-saved-disas.txt
Description: Text document


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