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[roland at sourceware dot org]

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http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=b0350db9747d602158377af3cf8ceb70764ea840

commit b0350db9747d602158377af3cf8ceb70764ea840
Author: Roland McGrath <roland@hack.frob.com>
Date:   Fri Aug 30 11:16:52 2013 -0700

    Use sfi_* macros in armv6t2 strlen.

diff --git a/ports/ChangeLog.arm b/ports/ChangeLog.arm
index 1806b08..8ef09b1 100644
--- a/ports/ChangeLog.arm
+++ b/ports/ChangeLog.arm
@@ -1,5 +1,7 @@
 2013-08-30  Roland McGrath  <roland@hack.frob.com>
 
+	* sysdeps/arm/armv6t2/strlen.S: Use sfi_pld and sfi_breg macros.
+
 	* sysdeps/arm/armv6t2/strlen.S: Include <arm-features.h> first thing.
 	[NO_THUMB]: Adapt code for ARM mode.
 
diff --git a/ports/sysdeps/arm/armv6t2/strlen.S b/ports/sysdeps/arm/armv6t2/strlen.S
index 4652c20..f2b3ab4 100644
--- a/ports/sysdeps/arm/armv6t2/strlen.S
+++ b/ports/sysdeps/arm/armv6t2/strlen.S
@@ -67,7 +67,7 @@
 	.text
 	.p2align 6
 ENTRY(strlen)
-	pld	[srcin, #0]
+	sfi_pld	srcin, #0
 	strd	r4, r5, [sp, #-8]!
 	cfi_adjust_cfa_offset (8)
 	cfi_rel_offset (r4, 0)
@@ -76,14 +76,15 @@ ENTRY(strlen)
 	bic	src, srcin, #7
 	mvn	const_m1, #0
 	ands	tmp1, srcin, #7		/* (8 - bytes) to alignment.  */
-	pld	[src, #32]
+	sfi_pld	src, #32
 	bne.w	.Lmisaligned8
 	mov	const_0, #0
 	mov	result, #-8
 .Lloop_aligned:
 	/* Bytes 0-7.  */
-	ldrd	data1a, data1b, [src]
-	pld	[src, #64]
+	sfi_breg src, \
+	ldrd	data1a, data1b, [\B]
+	sfi_pld	src, #64
 	add	result, result, #8
 .Lstart_realigned:
 	uadd8	data1a, data1a, const_m1	/* Saturating GE<0:3> set.  */
@@ -93,7 +94,8 @@ ENTRY(strlen)
 	cbnz	data1b, .Lnull_found
 
 	/* Bytes 8-15.  */
-	ldrd	data1a, data1b, [src, #8]
+	sfi_breg src, \
+	ldrd	data1a, data1b, [\B, #8]
 	uadd8	data1a, data1a, const_m1	/* Saturating GE<0:3> set.  */
 	add	result, result, #8
 	sel	data1a, const_0, const_m1	/* Select based on GE<0:3>.  */
@@ -102,7 +104,8 @@ ENTRY(strlen)
 	cbnz	data1b, .Lnull_found
 
 	/* Bytes 16-23.  */
-	ldrd	data1a, data1b, [src, #16]
+	sfi_breg src, \
+	ldrd	data1a, data1b, [\B, #16]
 	uadd8	data1a, data1a, const_m1	/* Saturating GE<0:3> set.  */
 	add	result, result, #8
 	sel	data1a, const_0, const_m1	/* Select based on GE<0:3>.  */
@@ -111,7 +114,8 @@ ENTRY(strlen)
 	cbnz	data1b, .Lnull_found
 
 	/* Bytes 24-31.  */
-	ldrd	data1a, data1b, [src, #24]
+	sfi_breg src, \
+	ldrd	data1a, data1b, [\B, #24]
 	add	src, src, #32
 	uadd8	data1a, data1a, const_m1	/* Saturating GE<0:3> set.  */
 	add	result, result, #8
@@ -139,12 +143,13 @@ ENTRY(strlen)
 
 .Lmisaligned8:
 	cfi_restore_state
-	ldrd	data1a, data1b, [src]
+	sfi_breg src, \
+	ldrd	data1a, data1b, [\B]
 	and	tmp2, tmp1, #3
 	rsb	result, tmp1, #0
 	lsl	tmp2, tmp2, #3			/* Bytes -> bits.  */
 	tst	tmp1, #4
-	pld	[src, #64]
+	sfi_pld	src, #64
 	S2HI	tmp2, const_m1, tmp2
 #ifdef NO_THUMB
 	mvn	tmp1, tmp2

http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=21bfcecf7a4ac3c150430a1a312268781c145414

commit 21bfcecf7a4ac3c150430a1a312268781c145414
Author: Roland McGrath <roland@hack.frob.com>
Date:   Fri Aug 30 10:43:39 2013 -0700

    Make armv6t2 strlen work in ARM mode too.

diff --git a/ports/ChangeLog.arm b/ports/ChangeLog.arm
index 2a95834..1806b08 100644
--- a/ports/ChangeLog.arm
+++ b/ports/ChangeLog.arm
@@ -1,3 +1,8 @@
+2013-08-30  Roland McGrath  <roland@hack.frob.com>
+
+	* sysdeps/arm/armv6t2/strlen.S: Include <arm-features.h> first thing.
+	[NO_THUMB]: Adapt code for ARM mode.
+
 2013-08-30  Will Newton  <will.newton@linaro.org>
 
 	[BZ #15909]
diff --git a/ports/sysdeps/arm/armv6t2/strlen.S b/ports/sysdeps/arm/armv6t2/strlen.S
index a52e2e7..4652c20 100644
--- a/ports/sysdeps/arm/armv6t2/strlen.S
+++ b/ports/sysdeps/arm/armv6t2/strlen.S
@@ -21,6 +21,7 @@
 
  */
 
+#include <arm-features.h>               /* This might #define NO_THUMB.  */
 #include <sysdep.h>
 
 #ifdef __ARMEB__
@@ -31,9 +32,24 @@
 #define S2HI		lsl
 #endif
 
-	/* This code requires Thumb.  */
+#ifndef NO_THUMB
+/* This code is best on Thumb.  */
 	.thumb
-	.syntax unified
+#else
+/* Using bne.w explicitly is desirable in Thumb mode because it helps
+   align the following label without a nop.  In ARM mode there is no
+   such difference.  */
+.macro bne.w label
+	bne \label
+.endm
+
+/* This clobbers the condition codes, which the real Thumb cbnz instruction
+   does not do.  But it doesn't matter for any of the uses here.  */
+.macro cbnz reg, label
+	cmp \reg, #0
+	bne \label
+.endm
+#endif
 
 /* Parameters and result.  */
 #define srcin		r0
@@ -130,9 +146,16 @@ ENTRY(strlen)
 	tst	tmp1, #4
 	pld	[src, #64]
 	S2HI	tmp2, const_m1, tmp2
+#ifdef NO_THUMB
+	mvn	tmp1, tmp2
+	orr	data1a, data1a, tmp1
+	itt	ne
+	orrne	data1b, data1b, tmp1
+#else
 	orn	data1a, data1a, tmp2
 	itt	ne
 	ornne	data1b, data1b, tmp2
+#endif
 	movne	data1a, const_m1
 	mov	const_0, #0
 	b	.Lstart_realigned

-----------------------------------------------------------------------

Summary of changes:
 ports/ChangeLog.arm                |    7 +++++
 ports/sysdeps/arm/armv6t2/strlen.S |   50 ++++++++++++++++++++++++++++--------
 2 files changed, 46 insertions(+), 11 deletions(-)


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