This is the mail archive of the libc-alpha@sourceware.org mailing list for the glibc project.

Index Nav:	[Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav:	[Date Prev] [Date Next]	[Thread Prev] [Thread Next]
Other format:	[Raw text]

PATCH: Define bit_SSE2 and index_SSE2

From: "H.J. Lu" <hongjiu dot lu at intel dot com>
To: "H.J. Lu" <hjl dot tools at gmail dot com>
Cc: GNU C Library <libc-alpha at sourceware dot org>
Date: Sun, 13 Dec 2009 11:24:29 -0800
Subject: PATCH: Define bit_SSE2 and index_SSE2
References: <20091209191818.GA8846@lucon.org>
Reply-to: "H.J. Lu" <hjl dot tools at gmail dot com>

On Wed, Dec 09, 2009 at 11:18:18AM -0800, H.J. Lu wrote:
> Hi,
> 
> This patch defines bit_XXX and index_XXX and use them to check processor
> feature in assembly code.  It can prevent typos in processor feature
> check.
> 

Hi,

This patch adds bit_SSE2 and index_SSE2 for 32bit assembly codes.

Thanks.


H.J.
---
2009-12-13  H.J. Lu  <hongjiu.lu@intel.com>

	* sysdeps/i386/i686/multiarch/strcspn.S Include <init-arch.h>
	instead of <ifunc-defines.h>.  Use bit_XXX and index_XXX to
	check processor feature.
	* sysdeps/i386/i686/multiarch/strlen.S: Likewise.
	* sysdeps/i386/i686/multiarch/strspn.S: Likewise.

	* sysdeps/x86_64/multiarch/init-arch.h (bit_SSE2): New.
	(index_SSE2): Likewise.

diff --git a/sysdeps/i386/i686/multiarch/strcspn.S b/sysdeps/i386/i686/multiarch/strcspn.S
index 73e7eb4..b2310e4 100644
--- a/sysdeps/i386/i686/multiarch/strcspn.S
+++ b/sysdeps/i386/i686/multiarch/strcspn.S
@@ -23,7 +23,7 @@
 #ifdef HAVE_SSE4_SUPPORT
 
 #include <sysdep.h>
-#include <ifunc-defines.h>
+#include <init-arch.h>
 
 #ifdef USE_AS_STRPBRK
 #define STRCSPN_SSE42	__strpbrk_sse42
@@ -64,7 +64,7 @@ ENTRY(STRCSPN)
 	jne	1f
 	call	__init_cpu_features
 1:	leal	STRCSPN_IA32@GOTOFF(%ebx), %eax
-	testl	$(1<<20), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET+__cpu_features@GOTOFF(%ebx)
+	testl	$bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
 	jz	2f
 	leal	STRCSPN_SSE42@GOTOFF(%ebx), %eax
 2:	popl	%ebx
@@ -80,7 +80,7 @@ ENTRY(STRCSPN)
 	jne	1f
 	call	__init_cpu_features
 1:	leal	STRCSPN_IA32, %eax
-	testl	$(1<<20), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET+__cpu_features
+	testl	$bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
 	jz	2f
 	leal	STRCSPN_SSE42, %eax
 2:	ret
diff --git a/sysdeps/i386/i686/multiarch/strlen.S b/sysdeps/i386/i686/multiarch/strlen.S
index 0c1e864..9786add 100644
--- a/sysdeps/i386/i686/multiarch/strlen.S
+++ b/sysdeps/i386/i686/multiarch/strlen.S
@@ -19,7 +19,7 @@
    02111-1307 USA.  */
 
 #include <sysdep.h>
-#include <ifunc-defines.h>
+#include <init-arch.h>
 
 /* Define multiple versions only for the definition in libc and for the
    DSO.  In static binaries, we need strlen before the initialization
@@ -46,7 +46,7 @@ ENTRY(strlen)
 	jne	1f
 	call	__init_cpu_features
 1:	leal	__strlen_ia32@GOTOFF(%ebx), %eax
-	testl	$(1<<26), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET+__cpu_features@GOTOFF(%ebx)
+	testl	$bit_SSE2, CPUID_OFFSET+index_SSE2+__cpu_features@GOTOFF(%ebx)
 	jz	2f
 	leal	__strlen_sse2@GOTOFF(%ebx), %eax
 2:	popl	%ebx
diff --git a/sysdeps/i386/i686/multiarch/strspn.S b/sysdeps/i386/i686/multiarch/strspn.S
index f306d2d..7fe6f97 100644
--- a/sysdeps/i386/i686/multiarch/strspn.S
+++ b/sysdeps/i386/i686/multiarch/strspn.S
@@ -23,7 +23,7 @@
 #ifdef HAVE_SSE4_SUPPORT
 
 #include <sysdep.h>
-#include <ifunc-defines.h>
+#include <init-arch.h>
 
 /* Define multiple versions only for the definition in libc.  */
 #ifndef NOT_IN_libc
@@ -49,7 +49,7 @@ ENTRY(strspn)
 	jne	1f
 	call	__init_cpu_features
 1:	leal	__strspn_ia32@GOTOFF(%ebx), %eax
-	testl	$(1<<20), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET+__cpu_features@GOTOFF(%ebx)
+	testl	$bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
 	jz	2f
 	leal	__strspn_sse42@GOTOFF(%ebx), %eax
 2:	popl	%ebx
@@ -65,7 +65,7 @@ ENTRY(strspn)
 	jne	1f
 	call	__init_cpu_features
 1:	leal	__strspn_ia32, %eax
-	testl	$(1<<20), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET+__cpu_features
+	testl	$index_SSE2, CPUID_OFFSET+index_SSE4_2+__cpu_features
 	jz	2f
 	leal	__strspn_sse42, %eax
 2:	ret
diff --git a/sysdeps/x86_64/multiarch/init-arch.h b/sysdeps/x86_64/multiarch/init-arch.h
index 9e8915f..0f8f77a 100644
--- a/sysdeps/x86_64/multiarch/init-arch.h
+++ b/sysdeps/x86_64/multiarch/init-arch.h
@@ -20,9 +20,11 @@
 
 #include <ifunc-defines.h>
 
+#define bit_SSE2	(1 << 26)
 #define bit_SSSE3	(1 << 9)
 #define bit_SSE4_2	(1 << 20)
 
+#define index_SSE2	COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET
 #define index_SSSE3	COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
 #define index_SSE4_2	COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET

References:
- PATCH: Define bit_XXX and index_XXX
  - From: H.J. Lu

Index Nav:	[Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav:	[Date Prev] [Date Next]	[Thread Prev] [Thread Next]