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[PATCH] [SH/SH4]: Defined _FPU_DOUBLE, _FPU_SINGLE, _FPU_RC_DOWN and _FPU_RC_UP
- From: Nobuhiro Iwamatsu <iwamatsu at nigauri dot org>
- To: libc-alpha at sourceware dot org
- Cc: Nobuhiro Iwamatsu <iwamatsu at nigauri dot org>
- Date: Thu, 26 Apr 2012 16:14:21 +0900
- Subject: [PATCH] [SH/SH4]: Defined _FPU_DOUBLE, _FPU_SINGLE, _FPU_RC_DOWN and _FPU_RC_UP
2012-04-26 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* sysdeps/sh/sh4/fpu/fpu_control.h (fesetround): Defined _FPU_DOUBLE,
_FPU_SINGLE, _FPU_RC_DOWN and _FPU_RC_UP. And add infomation for
fpscr register.
---
sysdeps/sh/sh4/fpu/fpu_control.h | 37 +++++++++++++++++++++++++++++++++++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/sysdeps/sh/sh4/fpu/fpu_control.h b/sysdeps/sh/sh4/fpu/fpu_control.h
index 1dfd697..8ce2988 100644
--- a/sysdeps/sh/sh4/fpu/fpu_control.h
+++ b/sysdeps/sh/sh4/fpu/fpu_control.h
@@ -1,5 +1,5 @@
/* FPU control word definitions. SH version.
- Copyright (C) 1999, 2000, 2009, 2010 Free Software Foundation, Inc.
+ Copyright (C) 1999-2012 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@@ -19,6 +19,32 @@
#ifndef _FPU_CONTROL_H
#define _FPU_CONTROL_H
+/*
+ * Renesas SH4 floating point control register bits.
+ *
+ * 31-22 -> reserved (read as 0, don't write 1)
+ * 21 -> FR bank bit
+ * 20 -> transfer size
+ * 0:32bit
+ * 1:32bit or 64bit
+ * 19 -> single or double
+ * 0: single
+ * 1: double
+ * 18 -> denormalizing mode
+ * 0: denormal number
+ * 1: denormal number is 0
+ * 17-12 -> Cause exception
+ * 11-7 -> Enable exception
+ * 6-2 -> Flag exception
+ * 1-0 -> Rounding Control
+ *
+ * Rounding Control:
+ * 00 - rounding to nearest (RN)
+ * 01 - rounding toward zero (RZ)
+ * 10 - Not support
+ * 11 - Not support
+ */
+
#include <features.h>
/* masking of interrupts */
@@ -29,8 +55,15 @@
#define _FPU_MASK_IM 0x0080 /* Inexact operation */
/* rounding control */
-#define _FPU_RC_NEAREST 0x0 /* RECOMMENDED */
+#define _FPU_RC_NEAREST 0x0 /* RECOMMENDED */
#define _FPU_RC_ZERO 0x1
+#define _FPU_RC_DOWN 0x0 /* DO NOT USE */
+#define _FPU_RC_UP 0x0 /* DO NOT USE */
+
+/* precision control */
+#define _FPU_EXTENDED 0x0
+#define _FPU_DOUBLE 0x80000
+#define _FPU_SINGLE 0x00000 /* When bit 19 was 0, single mode. */
#define _FPU_RESERVED 0xffc00000 /* These bits are reserved. */
--
1.7.10