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Re: [PATCH] Don't use SSE4_2 instructions on Intel Silvermont Micro Architecture.
- From: Dmitrieva Liubov <liubov dot dmitrieva at gmail dot com>
- To: "H.J. Lu" <hjl dot tools at gmail dot com>
- Cc: Siddhesh Poyarekar <siddhesh dot poyarekar at gmail dot com>, Ondřej Bílka <neleai at seznam dot cz>, Andi Kleen <andi at firstfloor dot org>, "Carlos O'Donell" <carlos at redhat dot com>, GNU C Library <libc-alpha at sourceware dot org>
- Date: Mon, 24 Jun 2013 11:34:44 +0400
- Subject: Re: [PATCH] Don't use SSE4_2 instructions on Intel Silvermont Micro Architecture.
- References: <CAHjhQ93zmP525hqW-2RnHBREc_949XLnm7sE-CSv3Nj8PQgUig at mail dot gmail dot com> <CAMe9rOqT31AFq1S3V0Krh2CZnHu=FiyXqhg840fimRtfU4_hXQ at mail dot gmail dot com> <20130618064910 dot GA19972 at domone dot kolej dot mff dot cuni dot cz> <CAHjhQ90Fc0kdZfQrUwLwpKbz2va4X9rzf1EkGD-s-RH-iF7guQ at mail dot gmail dot com> <CAHjhQ92qfjdKZthqAwxCVuCnLqDr2stdEbQpne5rKhzJPeN_cQ at mail dot gmail dot com> <51C23583 dot 1070307 at redhat dot com> <CAHjhQ93vWnCiVVU9MPoGptjQtn2J2PCDT2B7ZfXiKt+Cv_Rh_w at mail dot gmail dot com> <51C307A5 dot 7030608 at redhat dot com> <20130620151711 dot GA4891 at domone dot kolej dot mff dot cuni dot cz> <51C317AA dot 6080502 at redhat dot com> <20130621012427 dot GA4574 at domone dot kolej dot mff dot cuni dot cz> <CAAHN_R1HXyy0i25rtYKJ4Zox5u0R57xKbZDq=ZNf0BVm=7biMw at mail dot gmail dot com> <CAHjhQ92-+8YrGktq04XGySKyvAGU_ODHAPzEr8ot=jJjfiWYLg at mail dot gmail dot com> <CAMe9rOo4ejUxXsz9yrxb2M=aNGcXsuPac6MyRLBNa=x48RPfog at mail dot gmail dot com>
Yes, I will send next one for i386 when this is approved and committed.
-
Liubov
On Fri, Jun 21, 2013 at 8:13 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Fri, Jun 21, 2013 at 4:07 AM, Dmitrieva Liubov
> <liubov.dmitrieva@gmail.com> wrote:
>> I fixed the patch like H.J. suggested and attached results of micro
>> benchmarks you requested.
>>
>> The functions which were impacted are rawmemchr, strchr, strrchr,
>> strcmp, strcasecmp, strncmp, strncasecmp.
>> I see just some small regressions on small lengths but huge gains on
>> big lengths.
>>
>> Change Log.
>>
>> 2013-06-19 Liubov Dmitrieva <liubov.dmitrieva@intel.com>
>>
>> * sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features):
>> Set bit_Slow_SSE4_2 for Intel Silvermont architecture.
>> Set bit_Prefer_PMINUB_for_stringop for Intel Silvermont.
>> * sysdeps/x86_64/multiarch/init-arch.h: Define
>> bit_Slow_SSE4_2 and index_Slow_SSE4_2.
>> Define index_Prefer_PMINUB_for_stringop which was undefined.
>> * sysdeps/x86_64/multiarch/strchr.S: Use SSE2 version if
>> bit_Slow_SSE4_2 is on.
>> * sysdeps/x86_64/multiarch/strrchr.S: Use SSE2 version if
>> bit_Slow_SSE4_2 is on.
>> * sysdeps/x86_64/multiarch/strcmp.S: Use SSSE3 or SSE2 version if
>> bit_Slow_SSE4_2 is on.
>>
>>
>
> I assume you have another patch for i386.
>
>
> --
> H.J.