Update longlong.h from GCC

["Joseph S. Myers" <joseph at codesourcery dot com>]

I've applied this patch to update longlong.h from GCC so the two versions 
are in sync again.  This brings in two changes, both for architectures not 
supported by glibc:

2013-10-16  Hans-Peter Nilsson  <hp@axis.com>

	* longlong.h: Wrap the whole CRIS section in a single
	defined(__CRIS__) conditional.  Add comment about add_ssaaaa
	and sub_ddmmss.
	(COUNT_LEADING_ZEROS_0): Define when count_leading_zeros is
	defined.
	[__CRIS__] (__umulsidi3): Define.
	[__CRIS__] (umul_ppmm): Define in terms of __umulsidi3.

2013-10-01  Joern Rennecke  <joern.rennecke@embecosm.com>
	    Brendan Kehoe  <brendan@zen.org>
	    Simon Cook  <simon.cook@embecosm.com>

	* longlong.h [__arc__] (umul_ppmm): Remove.
	[__arc__] (__umulsidi3): Define.
	[__arc__ && __ARC_NORM__] (count_leading_zeroes): Define.
	[__arc__ && __ARC_NORM__] (COUNT_LEADING_ZEROS_0): Likewise.

diff --git a/ChangeLog b/ChangeLog
index cf60c77..3b5be23 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,5 +1,7 @@
 2013-12-04  Joseph Myers  <joseph@codesourcery.com>
 
+	* stdlib/longlong.h: Update from GCC.
+
 	[BZ #6807]
 	[BZ #15901]
 	* math/w_j0.c (y0): Raise FE_DIVBYZERO on zero argument.
diff --git a/stdlib/longlong.h b/stdlib/longlong.h
index c4b1b97..5f00e54 100644
--- a/stdlib/longlong.h
+++ b/stdlib/longlong.h
@@ -188,16 +188,20 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
 	     "rIJ" ((USItype) (bh)),					\
 	     "r" ((USItype) (al)),					\
 	     "rIJ" ((USItype) (bl)))
-/* Call libgcc routine.  */
-#define umul_ppmm(w1, w0, u, v) \
-do {									\
-  DWunion __w;								\
-  __w.ll = __umulsidi3 (u, v);						\
-  w1 = __w.s.high;							\
-  w0 = __w.s.low;							\
-} while (0)
-#define __umulsidi3 __umulsidi3
-UDItype __umulsidi3 (USItype, USItype);
+
+#define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
+#ifdef __ARC_NORM__
+#define count_leading_zeros(count, x) \
+  do									\
+    {									\
+      SItype c_;							\
+									\
+      __asm__ ("norm.f\t%0,%1\n\tmov.mi\t%0,-1" : "=r" (c_) : "r" (x) : "cc");\
+      (count) = c_ + 1;							\
+    }									\
+  while (0)
+#define COUNT_LEADING_ZEROS_0 32
+#endif
 #endif
 
 #if defined (__arm__) && (defined (__thumb2__) || !defined (__thumb__)) \
@@ -285,12 +289,39 @@ UDItype __umulsidi3 (USItype, USItype);
 
 #endif /* defined (__AVR__) */
 
-#if defined (__CRIS__) && __CRIS_arch_version >= 3
+#if defined (__CRIS__)
+
+#if __CRIS_arch_version >= 3
 #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
+#define COUNT_LEADING_ZEROS_0 32
+#endif /* __CRIS_arch_version >= 3 */
+
 #if __CRIS_arch_version >= 8
 #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
-#endif
-#endif /* __CRIS__ */
+#endif /* __CRIS_arch_version >= 8 */
+
+#if __CRIS_arch_version >= 10
+#define __umulsidi3(u,v) ((UDItype)(USItype) (u) * (UDItype)(USItype) (v))
+#else
+#define __umulsidi3 __umulsidi3
+extern UDItype __umulsidi3 (USItype, USItype);
+#endif /* __CRIS_arch_version >= 10 */
+
+#define umul_ppmm(w1, w0, u, v)		\
+  do {					\
+    UDItype __x = __umulsidi3 (u, v);	\
+    (w0) = (USItype) (__x);		\
+    (w1) = (USItype) (__x >> 32);	\
+  } while (0)
+
+/* FIXME: defining add_ssaaaa and sub_ddmmss should be advantageous for
+   DFmode ("double" intrinsics, avoiding two of the three insns handling
+   carry), but defining them as open-code C composing and doing the
+   operation in DImode (UDImode) shows that the DImode needs work:
+   register pressure from requiring neighboring registers and the
+   traffic to and from them come to dominate, in the 4.7 series.  */
+
+#endif /* defined (__CRIS__) */
 
 #if defined (__hppa) && W_TYPE_SIZE == 32
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \

-- 
Joseph S. Myers
joseph@codesourcery.com