Re: pthread_once on ARM SMP

["Carlos O'Donell" <carlos at redhat dot com>]

On 10/15/2013 02:49 PM, Jan Klötzke wrote:
>> Remember that ARM does not have a weakly ordered memory
>> model like Power, where it really is important to get all the
>> barriers in the right places.
> 
> AFAIU ARMv7 (like Cortex A9 or A15) actually has a weakly ordered memory 
> model. The CPU might reorder reads and writes (in the absence of memory 
> barriers) and might do speculative reads too. I don't know the Power memory 
> model by heart but AFAIK the ARMv7 memory model is quite close. [1]

I don't know if that's entirely true. I think that the ARMv7 architecture
reference only mandates weakly ordered but in principle no implementation
is weakly ordered. Therefore while the implementation of pthread_once is not
strictly correct it still works. Eventually it will be incorrect for an
implementation that is actually weakly ordered like Power.

Remember that what the architecture reference says for ARM is like a
standard of what should-be but not what is for the actual device that was
implemented by the licensee. So no ARMv7 device will have anything weaker
than what is described by ARM.
 
>> See the Power implementation for a "always correct" implementation.
>>
>> Either way Torvald Riegel is rewriting all of the pthread_once
>> implementations and unifying them:
>>
>> https://sourceware.org/ml/libc-alpha/2013-10/msg00257.html
>>
>> https://sourceware.org/ml/libc-alpha/2013-10/msg00416.html
>>
>> https://sourceware.org/ml/libc-alpha/2013-10/msg00415.html
> 
> This looks good. The unified implementation is what I would have expected on 
> ARM too.

Please feel free to help in the review effort. We're going to try
get all of the architectures onto the unified implmentation which is
easier to review and audit.

Cheers,
Carlos.