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Re: [patch, mips] Improved memset for MIPS
- From: "Carlos O'Donell" <carlos at systemhalted dot org>
- To: Andrew Pinski <pinskia at gmail dot com>
- Cc: Steve Ellcey <sellcey at mips dot com>, "Joseph S. Myers" <joseph at codesourcery dot com>, "Carlos O'Donell" <carlos at redhat dot com>, "libc-ports at sourceware dot org" <libc-ports at sourceware dot org>
- Date: Thu, 12 Dec 2013 19:01:51 -0500
- Subject: Re: [patch, mips] Improved memset for MIPS
- Authentication-results: sourceware.org; auth=none
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On Thu, Dec 12, 2013 at 5:19 PM, Andrew Pinski <pinskia@gmail.com> wrote:
> On Fri, Sep 20, 2013 at 10:32 AM, Steve Ellcey <sellcey@mips.com> wrote:
>> On Fri, 2013-09-20 at 16:43 +0000, Joseph S. Myers wrote:
>>> On Wed, 18 Sep 2013, Steve Ellcey wrote:
>>>
>>> > 2013-09-18 Steve Ellcey <sellcey@mips.com>
>>> >
>>> > * sysdeps/mips/memset.S: Change prefetching and add loop unrolling.
>>> > * sysdeps/mips/mips64/memset.S: Remove.
>>>
>>> OK, though I believe "proAptive" in a comment should be "proAptiv".
>>
>> You are right. I fixed that and checked in the patch.
>
>
> I noticed this patch causes some performance regressions on Octeon due
> to having 128 byte cache lines.
> Changing PREFETCH_CHUNK/PREFETCH_FOR_STORE to assume 128 byte cache
> line gives us the performance back and improves over the original code
> at least 15%.
> That is:
> # define PREFETCH_CHUNK 128
> # define PREFETCH_FOR_STORE(chunk, reg) \
> pref PREFETCH_STORE_HINT, (chunk)*128(reg);
Submit a patch for that?
We have microbenchmarks now, but the next hardest
part is going to be archiving data by device so that
the community can help track performance and point
out regressions like this.
Cheers,
Carlos.