modeling latency (fwd)

[Ben Elliston]

  FChE> "hops" are not very meaningful.  "cycles" and "time" are, and may be
  FChE> converted one-to-one by some knowledgeable component.

Right.

  [...]

  FChE> (ditto, to account for cache hit times & miss penalties), all the way
  FChE> to the CPU.  (The "sid::bus::delayed" indication can finally die.)

What was the intention of the delayed indication?  Current usage in
the source tree indicates that it is not quite used to model latency.
For example, the gloss component spins in a loop while the target
memory is not ready to accept a write.

Can you explain the rationale behind the origins of bus::delayed and
how you see that we can live without it?

I did not try to cover this potential change in my recent check-in.  I
felt this is a separate change that should be tacked separately.

Ben