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Re: [PATCH] Linux Kernel Markers
- From: Richard J Moore <richardj_moore at uk dot ibm dot com>
- To: Alan Cox <alan at lxorguk dot ukuu dot org dot uk>
- Cc: Andrew Morton <akpm at osdl dot org>, Mathieu Desnoyers <compudj at krystal dot dyndns dot org>, "Frank Ch. Eigler" <fche at redhat dot com>, Greg Kroah-Hartman <gregkh at suse dot de>, Christoph Hellwig <hch at infradead dot org>, Jes Sorensen <jes at sgi dot com>, karim at opersys dot com, Paul Mundt <lethal at linux-sh dot org>, linux-kernel <linux-kernel at vger dot kernel dot org>, ltt-dev at shafik dot org, Martin Bligh <mbligh at google dot com>, Michel Dagenais <michel dot dagenais at polymtl dot ca>, Ingo Molnar <mingo at elte dot hu>, prasanna at in dot ibm dot com, systemtap at sources dot redhat dot com, Thomas Gleixner <tglx at linutronix dot de>, William Cohen <wcohen at redhat dot com>, Tom Zanussi <zanussi at us dot ibm dot com>
- Date: Thu, 21 Sep 2006 00:00:41 +0100
- Subject: Re: [PATCH] Linux Kernel Markers
Alan Cox <alan@lxorguk.ukuu.org.uk> wrote on 20/09/2006 11:44:29:
> Ar Maw, 2006-09-19 am 20:52 -0400, ysgrifennodd Karim Yaghmour:
> > a) the errata & a possible thread having an IP leading back within (not
> > at the start of) the range to be replaced.
> > b) the errata & replacing single instruction with single instruction of
> > same size.
>
> Intel don't distinguish. Richard's reply later in the thread answers a
> lot more including what Intels architecture team said about int3 being a
> specific safe case for soem reason
>
> > I was vaguely aware of the issue on x86. Do you know if this applies
the
> > same on other achitectures?
>
> I wouldn't know.
It can for another reason - score-boarding: that's where a byte being
stored assumes intermediate values due to the bits not being set
simultaneously. Generally this doesn't cause a problem because data across
processors is serialised for update by mutexes. However, when applied to
code all sorts of interesting instructions can execute before the bits
settle down. I haven't heard of this troubling Intel, but it does occur on
some current architectures.
Richard