How to handle MIPS-like general register 0?

[Frank Ch. Eigler]

greg@mcgary.org (Greg McGary) writes:

: What's the recommended way of handling simulator semantics for a
: general register zero that always reads as 0, and writes as bit-bucket
: (as for MIPS)?  [...]

Another way is to add an explicit register-setting statement into each
iteration of the instruction evaluation loop.  One trades the cost of
a conditional branch (by intercepting the register-setting hooks) for
the cost of fixed overhead (always clearing the sucker).

- FChE