how can one achieve pipelined operation?

[Frank Ch. Eigler]

Hi -

On Thu, Jul 02, 2009 at 09:44:54AM -0700, Joseph A wrote:
> As was suggested I have been trying to implement a pipeline with the (delay N
> (set ... ...)) directive using the directions given in the [RFA:] Fix
> breakage of manually building SID CPU thread, however my port has multiple
> ISAs.

OK.

> I get two errors which say "error: invalid initialization of
> reference of type '%ISA1%::write_stacks&' from expression of type
> '%CPU%::write_stacks'" and "error: invalid initialization of
> reference of type '%ISA2%::write_stacks&' from expression of type
> '%CPU%::write_stacks'".  Also, the machine generated reset() and
> writeback() functions are empty.

These don't sound familiar to me.  I can only advise that you refer to
the sid simulator pieces generated & hand-written for other
exposed-pipeline ports (mt, sh/*).

- FChE