Make question

Emmanuel STAPF
Tue Jan 25 07:35:00 GMT 2000

In my makefile, I have the following statement:

	$(CC) $(CFLAGS) -c $<

and I'm using my makefile to generate a `file.obj' from a `file.c' which
will be using to create a `library.lib' file.

However, make fails with the following output:
make: *** No rule to make target `file.obj', needed by `library.lib'.  Stop.

Is there something special to do to allow my implicit rule.

Thanks in advance,

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